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AT90PWM2 Datasheet(PDF) 180 Page - ATMEL Corporation |
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AT90PWM2 Datasheet(HTML) 180 Page - ATMEL Corporation |
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180 / 365 page  180 AT90PWM2/3 4317A-3–AVR–02/05 PSC0 Interrupt Flag Register – PIFR0 PSC1 Interrupt Flag Register – PIFR1 PSC2 Interrupt Flag Register – PIFR2 • Bit 7 – POACnB : PSC n Output B Activity This bit is set by hardware each time the output PSCOUTn1 changes from 0 to 1 or from 1 to 0. Must be cleared by software by writing a one to its location. This feature is useful to detect that a PSC output doesn’t change due to a freezen exter- nal input signal. • Bit 6 – POACnA : PSC n Output A Activity This bit is set by hardware each time the output PSCOUTn0 changes from 0 to 1 or from 1 to 0. Must be cleared by software by writing a one to its location. This feature is useful to detect that a PSC output doesn’t change due to a freezen exter- nal input signal. • Bit 5 – PSEIn : PSC n Synchro Error Interrupt This bit is set by hardware when the update (or end of PSC cycle) of the PSCn config- ured in auto run (PARUNn = 1) does not occur at the same time than the PSCn-1 which has generated the input run signal. (For PSC0, PSCn-1 is PSC2). Must be cleared by software by writing a one to its location. This feature is useful to detect that a PSC doesn’t run at the same speed or with the same phase than the PSC master. • Bit 4 – PEVnB : PSC n External Event B Interrupt This bit is set by hardware when an external event which can generates a capture or a retrigger from Retrigger/Fault block B occurs. Must be cleared by software by writing a one to its location. This bit can be read even if the corresponding interrupt is not enabled (PEVEnB bit = 0). Bit 7 65 43 21 0 POAC0B POAC0A PSEI0 PEV0B PEV0A PRN01 PRN00 PEOP2 PIFR0 Read/Write R R R/W R/W R/W R R R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 65 43 21 0 POAC1B POAC1A PSEI1 PEV1B PEV1A PRN11 PRN10 PEOP1 PIFR1 Read/Write R R R/W R/W R/W R R R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 65 43 21 0 POAC2B POAC2A PSEI2 PEV2B PEV2A PRN21 PRN20 PEOP2 PIFR2 Read/Write R R R/W R/W R/W R R R/W Initial Value 0 0 0 0 0 0 0 0 |
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