AT90PWM2 datasheet(233/365 Pages) ATMEL

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AT90PWM2/3

4317B–AVR–02/05

EUSART Control Register B –

EUCSRB

• Bit 7:5 –Reserved Bits

These bits are reserved for future use. For compatibilty with future devices, these bits

must be written to zero when EUSCRB is written.

• Bit 4 – EUSART Enable Bit

Set to enable the EUSART mode, clear to operate as standard USART.

• Bit 3– EUSBS Enable Bit

This bit selects the number of stop bits detected by the receiver.

Note:

The number of stop bit inserted by the Transmitter in EUSART mode is configurable

throught the USBS bit of in the of the USART.

• Bit 2–Reserved Bit

This bit is reserved for future use. For compatibilty with future devices, this bit must be

written to zero when EUSCRB is written.

• Bit 1 – Manchester mode

When set the EUSART operates in manchester encoder/decoder mode (Manchester

encoded frames). When cleared the EUSART detected and transmit level encoded

frames.

Reserved

16 OR 17 bit (for Manchester

encoded only mode)

111

17-bit

Table 88. URxS Bits Settings

URxS3

URxS2

URxS1

URxS0

Receive Character Size

Bit

765

432

EUSART

EUSBS

EMCH

BODR

EUCSRB

Read/Write

R/W

Initial Value

000

Table 89. EUSBS Bit Settings

EUSBS

Receiver Stop Bit(s)

01-bit

12-bit

Table 90. USART/EUSART modes selection summary

UMSEL

EMCH

EUSART

Mode

Asynchronous up to 9 bits level encoded (standard

asynchronous USART mode)

Synchronous up to 9 bits level encoded (standard

synchronous USART mode)

Asynchronous up to 17 bits level encoded

AT90PWM2 Datasheet(PDF) 233 Page - ATMEL Corporation

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