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AT90PWM2 Datasheet(PDF) 234 Page - ATMEL Corporation

Part # AT90PWM2
Description  8-bit Microcontroller with 8K Bytes In-System Programmable Flash
PDF  365 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT90PWM2 Datasheet(HTML) 234 Page - ATMEL Corporation

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234
AT90PWM2/3
4317B–AVR–02/05
As in Manchester mode the parity checker and generator are unavailable, the parity
should be configured to none ( write UPM1:0 to 00 in UCSRC), see Table 79.
• Bit 0 –Bit Order
This bit allows to change the bit ordering in the transmit and received frames.
Clear to transmit and receive LSB first (standard USART mode)
Set to transmit and receive MSB first.
EUSART Status Register C –
EUCSRC
• Bit 7:4 –Reserved Bits
These bits are reserved for future use. For compatibilty with future devices, these bits
must be written to zero when EUSCRC is written.
• Bit 3 –Frame Error Manchester
This bit is set by hardware when a framing error is detected in manchester mode. This
bit is valid when the RxC bit is set and until the receive buffer (UDR) is read.
• Bit 2 –F1617
When the receiver is configured for 16 or 17 bits in Manchester encoded mode, this bit
indicates if the received frame is 16 or 17 bits lenght.
Cleared: indicates that the received frame is 16 bits lenght.
Set: Indicates that the received frame is 17 bits lenght.
This bit is valid when the RxC bit is set and until the receive buffer (UDR) is read.
• Bit 1:0 –Stop bits values
When Manchester mode is activated, these bits contains the stop bits value of the previ-
ous received frame.
When the data bits in the serial frame are standard level encoded, these bits are not
updated.
Manchester receiver Baud
Rate Registers – MUBRRL and
MUBRRH
0
1
1
Asynchronous up to 17 bits Manchester encoded
1
0
1
Synchronous up to 17 bits level encoded
11
1
Reserved
Table 90. USART/EUSART modes selection summary
UMSEL
EMCH
EUSART
Mode
Bit
765
432
10
-
---
FEM
F1617
STP1
STP0
EUCSRC
Read/Write
RR
RRR
RRR
Initial Value
000
000
00
Bit
1514
13
1211
10
9
8
MUBRR[15:8]
MUBRRH
MUBRR[7:0]
MUBRRL
765
432
10
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
000
000
00
000
000
00



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