AT90PWM2 datasheet(239/365 Pages) ATMEL

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AT90PWM2/3

4317B–AVR–02/05

These 2 bits determine the sensitivity of the interrupt trigger.

The different setting are shown in Table 92.

• Bit 3– AC1ICE: Analog Comparator 1 Interrupt Capture Enable bit

Set this bit to enable the input capture of the Timer/Counter1 on the analog comparator

event. The comparator output is in this case directly connected to the input capture

front-end logic, making the comparator utilize the noise canceler and edge select fea-

tures of the Timer/Counter1 Input Capture interrupt. To make the comparator trigger the

Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask Regis-

ter (TIMSK1) must be set.

In case ICES1 bit (“Timer/Counter1 Control Register B – TCCR1B” on page 127) is set

high, the rising edge of AC1O is the capture/trigger event of the Timer/Counter1, in case

ICES1 is set to zero, it is the falling edge which is taken into account.

Clear this bit to disable this function. In this case, no connection between the Analog

Comparator and the input capture function exists.

• Bit 2, 1, 0– AC1M2, AC1M1, AC1M0: Analog Comparator 1 Multiplexer register

These 3 bits determine the input of the negative input of the analog comparator.

The different setting are shown in Table 95.

Analog Comparator 2 Control

• Bit 7– AC2EN: Analog Comparator 2 Enable Bit

Set this bit to enable the analog comparator 2.

Clear this bit to disable the analog comparator 2.

Table 94. Interrupt sensitivity selection

AC1IS1

AC1IS0

Description

Comparator Interrupt on output toggle

Reserved

Comparator interrupt on output falling edge

Comparator interrupt on output rising edge

Table 95. Analog Comparator 1 negative input selection

AC1M2

AC1M1

AC1M0

Description

“Vref”/6.40

“Vref”/3.20

“Vref”/2.13

“Vref”/1.60

Analog Comparator Negative Input (ACMPM pin)

DAC result

Reserved

Bit

AC2EN

AC2IE

AC2IS1

AC2IS0

AC2M2

AC2M1

AC2M0

AC2CON

Read/Write

R/W

Initial Value

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