AT90PWM2 datasheet(248/365 Pages) ATMEL

248 / 365 page

248

AT90PWM2/3

4317B–AVR–02/05

Figure 120. ADC Timing Diagram, Auto Triggered Conversion

Figure 121. ADC Timing Diagram, Free Running Conversion

Changing Channel or

Reference Selection

The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a tem-

porary register to which the CPU has random access. This ensures that the channels

and reference selection only takes place at a safe point during the conversion. The

channel and reference selection is continuously updated until a conversion is started.

Once the conversion starts, the channel and reference selection is locked to ensure a

sufficient sampling time for the ADC. Continuous updating resumes in the last ADC

clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the

conversion starts on the following rising ADC clock edge after ADSC is written. The user

is thus advised not to write new channel or reference selection values to ADMUX until

one ADC clock cycle after ADSC is written.

Table 98. ADC Conversion Time

Condition

First

Conversion

Normal

Conversion,

Single Ended

Auto Triggered

Conversion

Sample & Hold

(Cycles from Start of Conversion)

13.5

3.5

Conversion Time

(Cycles)

15.5

Sign and MSB of Result

LSB of Result

ADC Clock

Trigger

Source

ADIF

ADCH

ADCL

Cycle Number

One Conversion

Next Conversion

Conversion

Complete

Prescaler

Reset

ADATE

Prescaler

Reset

Sample &

Hold

MUX and REFS

Update

Sign and MSB of Result

LSB of Result

ADC Clock

ADSC

ADIF

ADCH

ADCL

Cycle Number

One Conversion

Next Conversion

Conversion

Complete

Sample & Hold

MUX and REFS

Update

AT90PWM2 Datasheet(PDF) 248 Page - ATMEL Corporation

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