AT90PWM2 datasheet(249/365 Pages) ATMEL

249 / 365 page

249

AT90PWM2/3

4317B–AVR–02/05

If Auto Triggering is used, the exact time of the triggering event can be indeterministic.

Special care must be taken when updating the ADMUX Register, in order to control

which conversion will be affected by the new settings.

If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If

the ADMUX Register is changed in this period, the user cannot tell if the next conversion

is based on the old or the new settings. ADMUX can be safely updated in the following

ways:

When ADATE or ADEN is cleared.

During conversion, minimum one ADC clock cycle after the trigger event.

After a conversion, before the interrupt flag used as trigger source is cleared.

When updating ADMUX in one of these conditions, the new settings will affect the next

ADC conversion.

In order to start a conversion on an amplified channel, there is a dedicated ADASCR bit

in ADCSRB register which wait for the next amplifier trigger event before really starting

the conversion by an hardware setting of the ADSC bit in ADCSRA register.

ADC Input Channels

When changing channel selections, the user should observe the following guidelines to

ensure that the correct channel is selected:

•

In Single Conversion mode, always select the channel before starting the

conversion. The channel selection may be changed one ADC clock cycle after

writing one to ADSC. However, the simplest method is to wait for the conversion to

complete before changing the channel selection.

•

In Free Running mode, always select the channel before starting the first

conversion. The channel selection may be changed one ADC clock cycle after

writing one to ADSC. However, the simplest method is to wait for the first conversion

to complete, and then change the channel selection. Since the next conversion has

already started automatically, the next result will reflect the previous channel

selection. Subsequent conversions will reflect the new channel selection.

•

In Free Running mode, because the amplifier clear the ADSC bit at the end of an

amplified conversion, it is not possible to use the free running mode, unless ADSC

bit is set again by soft at the end of each conversion.

ADC Voltage Reference

The reference voltage for the ADC (V

REF) indicates the conversion range for the ADC.

Single ended channels that exceed V

REF will result in codes close to 0x3FF. VREF can be

selected as either AV

CC, internal 2.56V reference, or external AREF pin.

CC is connected to the ADC through a passive switch. The internal 2.56V reference is

generated from the internal bandgap reference (V

BG) through an internal amplifier. In

either case, the external AREF pin is directly connected to the ADC, and the reference

voltage can be made more immune to noise by connecting a capacitor between the

AREF pin and ground. V

REF can also be measured at the AREF pin with a high impedant

voltmeter. Note that V

REF is a high impedant source, and only a capacitive load should

be connected in a system.

If the user has a fixed voltage source connected to the AREF pin, the user may not use

the other reference voltage options in the application, as they will be shorted to the

external voltage. If no external voltage is applied to the AREF pin, the user may switch

between AV

CC and 2.56V as reference selection. The first ADC conversion result after

switching reference voltage source may be inaccurate, and the user is advised to dis-

card this result.

AT90PWM2 Datasheet(PDF) 249 Page - ATMEL Corporation

AT90PWM2 Datasheet(HTML) 249 Page - ATMEL Corporation

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