AT90PWM2 datasheet(283/365 Pages) ATMEL

283 / 365 page

283

AT90PWM2/3

4317B–AVR–02/05

When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM

instruction is executed within three cycles after the BLBSET and SELFPRGEN bits are

set in the SPMCSR, the value of the Extended Fuse byte (EFB) will be loaded in the

destination register as shown below. Refer to Table 120 on page 289 for detailed

description and mapping of the Extended Fuse byte.

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that

are unprogrammed, will be read as one.

Preventing Flash Corruption

During periods of low V

CC, the Flash program can be corrupted because the supply volt-

age is too low for the CPU and the Flash to operate properly. These issues are the same

as for board level systems using the Flash, and the same design solutions should be

applied.

A Flash program corruption can be caused by two situations when the voltage is too low.

First, a regular write sequence to the Flash requires a minimum voltage to operate cor-

rectly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage

for executing instructions is too low.

Flash corruption can easily be avoided by following these design recommendations (one

is sufficient):

If there is no need for a Boot Loader update in the system, program the Boot

Loader Lock bits to prevent any Boot Loader software updates.

Keep the AVR RESET active (low) during periods of insufficient power supply

voltage. This can be done by enabling the internal Brown-out Detector (BOD) if

the operating voltage matches the detection level. If not, an external low V

reset protection circuit can be used. If a reset occurs while a write operation is in

progress, the write operation will be completed provided that the power supply

voltage is sufficient.

Keep the AVR core in Power-down sleep mode during periods of low V

CC. This

will prevent the CPU from attempting to decode and execute instructions, effec-

tively protecting the SPMCSR Register and thus the Flash from unintentional

writes.

Programming Time for Flash

when Using SPM

The calibrated RC Oscillator is used to time Flash accesses. Table 113 shows the typi-

cal programming time for Flash accesses from the CPU.

Bit

–

EFB3

EFB2

EFB1

EFB0

Table 113. SPM Programming Time

Symbol

Min Programming Time

Max Programming Time

Flash write (Page Erase, Page Write,

and write Lock bits by SPM)

3.7 ms

4.5 ms

AT90PWM2 Datasheet(PDF) 283 Page - ATMEL Corporation

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