ADGS1209 datasheet(9/33 Pages) AD

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Data Sheet

ADGS1208/ADGS1209

Rev. 0 | Page 9 of 33

TIMING CHARACTERISTICS

VL = 2.7 V to 5.5 V, GND = 0 V, and all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization,

not production tested.

Table 5.

Parameter

Limit

Unit

Test Conditions/Comments

TIMING CHARACTERISTICS

ns min

SCLK or CNV period

ns min

SCLK or CNV high pulse width

ns min

SCLK or CNV low pulse width

ns min

CS falling edge to SCLK or CNV active edge

ns min

Data setup time

ns min

Data hold time

ns min

SCLK or CNV active edge to CS rising edge

ns max

CS falling edge to SDO data available

t91

ns max

SCLK falling edge to SDO data available

t10

ns max

CS rising edge to SDO returns to high impedance

t11

ns min

CS high time between SPI commands

t12

ns min

CS falling edge to SCLK or CNV edge rejection

t13

ns min

CS rising edge to SCLK or CNV edge rejection

Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. t9 determines the maximum SCLK frequency when SDO is used.

Timing Diagrams

t10

R/W

SCLK

SDI

SDO

Figure 3. Address Mode Timing Diagram

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