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ADGS1209 Datasheet(PDF) 24 Page - Analog Devices

Part # ADGS1209
Description  SPI Interface, Low CON and QINJ, 짹15 V/12 V, 1.8 V Logic Control, 8:1/Dual 4:1 Mux Switches
PDF  33 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADGS1209 Datasheet(HTML) 24 Page - Analog Devices

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ADGS1208/ADGS1209
Data Sheet
Rev. 0 | Page 24 of 33
The ADGS1208/ADGS1209 can only enter daisy-chain mode
when in address mode by sending the 16-bit SPI command,
0x2500 (see Figure 50). When the ADGS1208/ADGS1209
receive this command, the SDO of the device sends out the
same command because the alignment bits at SDO are 0x25,
which allows multiple daisy-connected devices to enter daisy-
chain mode in a single SPI frame. A hardware reset is required to
exit daisy-chain mode.
For the timing diagram of a typical daisy-chain SPI frame, see
Figure 51. When CS goes high, Device 1 writes Command 0,
Bits[7:0] to its switch data register, Device 2 writes Command 1,
Bits[7:0] to its switches, and so on. The SPI block uses the last
eight bits it received through SDI to update the switches. After
entering daisy chain mode, the first eight bits sent out by SDO
on each device in the chain are 0x00. When CS goes high, the
internal shift register value does not reset back to 0.
An SCLK rising edge reads in data on SDI while data is
propagated out of SDO on an SCLK falling edge. The expected
number of SCLK cycles must be a multiple of eight before CS
goes high. When this is not the case, the SPI interface sends the
last eight bits received to the switch data register.
POWER-ON RESET
The digital section of the ADGS1208/ADGS1209 goes through an
initialization phase during VL power up. This initialization also
occurs after a hardware or software reset. After VL power-up or
a reset, ensure that a minimum of 120 µs from the time of
power-up or reset before any SPI command is issued. Ensure
that VL does not drop out during the 120 µs initialization phase,
because it may result in incorrect operation of the
ADGS1208/ADGS1209.
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
SDO
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SDI
SCLK
CS
Figure 50. SPI Command to Enter Daisy-Chain Mode
SDO
COMMAND3[7:0]
8’h00
COMMAND2[7:0]
COMMAND3[7:0]
COMMAND1[7:0]
COMMAND2[7:0]
COMMAND0[7:0]
COMMAND1[7:0]
SDI
SDO3
8’h00
8’h00
8’h00
8’h00
COMMAND3[7:0]
8’h00
COMMAND2[7:0]
COMMAND3[7:0]
SDO2
DEVICE 2
DEVICE 1
DEVICE 4
DEVICE 3
CS
NOTES
1. SDO2 AND SDO3 ARE THE OUTPUT COMMANDS FROM DEVICE 2 AND DEVICE 3, RESPECTIVELY.
Figure 51. Example of an SPI Frame Where Four ADGS1208/ADGS1209 Devices Connect in Daisy-Chain Mode



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