AD9375BBCZ datasheet(57/61 Pages) AD

57 / 61 page

Data Sheet

AD9375

Rev. 0 | Page 57 of 61

SYNTHESIZERS

RF PLL

The AD9375 contains three fractional-N PLLs to generate the

RF LOs used by the transmitter, receiver, and observation

receiver. The PLL incorporates an internal VCO and loop filter

that require no external components. The internal VCO LDO

regulators eliminate the need for additional external power

supplies for the PLLs. These regulators only require an external

bypass capacitor for each supply.

Clock PLL

The AD9375 contains a PLL synthesizer that generates all of the

baseband related clock signals and SERDES clocks. This PLL is

programmed based on the data rate and sample rate requirements

of the system.

SERIAL PERIPHERAL INTERFACE (SPI)

The AD9375 uses a SPI to communicate with the baseband

processor (BBP). This interface can be configured as a 4-wire

interface with dedicated receive and transmit ports, or it can be

configured as a 3-wire interface with a bidirectional data

communications port. This bus allows the BBP to set all device

control parameters using a simple address data serial bus protocol.

Write commands follow a 24-bit format. The first bit sets the

bus direction of the bus transfer. The next 15 bits set the address

where data is written. The final eight bits are the data being

transferred to the specific register address.

Read commands follow a similar format with the exception that

the first 16 bits are transferred on the SDIO pin, and the final

eight bits are read from the AD9375, either on the SDO pin in

4-wire mode or on the SDIO pin in 3-wire mode.

GPIO_x AND GPIO_3P3_x PINS

The AD9375 general-purpose input/output signals referenced

to the VDD_IF supply can be configured for numerous functions.

Some of these pins, when configured as outputs, are used by the

BBP as real-time signals to provide a number of internal settings

and measurements. This configuration allows the BBP to monitor

receiver performance in different situations. A pointer register

selects the information that is output to these pins. Signals used

for manual gain mode, calibration flags, state machine states,

and various receiver parameters are among the outputs that

can be monitored on these pins. In addition, certain pins can

be configured as inputs and used in various functions such as

setting the receiver gain in real time.

The GPIO_3P3_x pins are referenced to the VDDA_3P3 supply.

These pins can provide control signals to other components

such as voltage gain amplifiers (VGAs) or attenuators in the RF

section that typically use a higher reference voltage.

AUXILIARY CONVERTERS

Auxiliary ADC Inputs (AUXADC_x)

The AD9375 contains an auxiliary ADC that is multiplexed to four

input pins (AUXADC_0 through AUXADC_3). This block can

monitor system voltages without adding additional components.

The auxiliary ADC is 12 bits with an input voltage range of 0.05 V

to VDDA_3P3 − 0.05 V. When enabled, the auxiliary ADC is

free running. Software reads of the output value provide the last

value latched at the ADC output.

Auxiliary DACs (AUXDAC_x)

The AD9375 contains 10 identical auxiliary DACs (AUXDAC_0 to

AUXDAC_9) that can supply bias voltages, analog control voltages,

or other system functionality. The inputs of these auxiliary DACs

(AUXDAC_0 to AUXDAC_9) are multiplexed with the GPIO_

3P3_x pins according to Table 7. The auxiliary DACs are 10 bits,

have an output voltage range of approximately 0.5 V to 3.0 V,

and have a current drive of 10 mA.

Table 7. AUXDAC Input Pin Assignments

AUXDAC_x Output

GPIO_3P3_x Pin

AUXDAC_0

GPIO_3P3_9

AUXDAC_1

GPIO_3P3_7

AUXDAC_2

GPIO_3P3_6

AUXDAC_3

GPIO_3P3_10

AUXDAC_4

GPIO_3P3_0

AUXDAC_5

GPIO_3P3_1

AUXDAC_6

GPIO_3P3_3

AUXDAC_7

GPIO_3P3_4

AUXDAC_8

GPIO_3P3_5

AUXDAC_9

GPIO_3P3_8

AD9375BBCZ Datasheet(PDF) 57 Page - Analog Devices

AD9375BBCZ Datasheet(HTML) 57 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

Datasheet Download

Link URL