AD9375BBCZ datasheet(58/61 Pages) AD

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AD9375

Data Sheet

Rev. 0 | Page 58 of 61

JESD204B DATA INTERFACE

The digital data interface for the AD9375 uses JEDEC Standard

JESD204B Subclass 1. The serial interface operates at speeds of

up to 6144 Mbps. The benefits of the JESD204B interface

include a reduction in required board area for data interface

routing and smaller package options due to the need for fewer

pins. Digital filtering is included in all receiver and transmitter

paths to provide proper signal conditioning and sampling rates

to meet the JESD204B data requirements. Examples of the

digital filtering configurations for the Tx and Rx paths are

shown in Figure 230 and Figure 231, respectively.

POWER SUPPLY SEQUENCE

The AD9375 requires a specific power-up sequence to avoid

undesired power-up currents. The optimal power-on sequence

starts the process by powering up the VDIG and the VDDA_1P3

(analog) supplies simultaneously. If they cannot power up

simultaneously, the VDIG supply must power up first. The

VDDA_3P3, VDDA_1P8, and JESD_VTT_DES supplies must

then power up after the VDIG and VDDA_1P3 supplies. Note

that the VDD_IF supply can power up at any time. It is also

recommended to toggle the RESET signal after power has

stabilized prior to configuration. Follow the reverse order of

the power-up sequence to power down.

Table 8. Example Rx/Tx Interface Rates (Two Rx/Two Tx Channels, Maximum JESD204B Lane Rates)

Tx/Tx Synthesis/

Rx Bandwidth (MHz)

Tx Input

Rate (MSPS)

Rx Output

Rate (MSPS)

JESD204B Lane Rate

(Mbps), Two Tx/Two Rx

JESD204B (No.

of Lanes) Tx/Rx

Reference Clock Options (MHz)

100/250/100

307.2

153.6

6144

4/2

122.88, 153.6, 245.76, 307.2

75/200/100

245.76

122.88

4915.2

4/2

122.88, 245.76

20/100/40

122.88

61.44

2457.6

4/2

122.88, 245.76

20/100/20

122.88

30.72

2457.6

4/1

122.88, 245.76

I/Q DAC

TRANSMITTER FIR

(INTERPOLATION

1, 2, 4)

DIGITAL

GAIN

JESD204B

QUADRATURE

ERROR

CORRECTION

DPD

ACTUATOR

TRANSMITTER

HALF-BAND

FILTER 0

(DPD)

TRANSMITTER

HALF-BAND

FILTER 2

TRANSMITTER

HALF-BAND

FILTER 1

Figure 230. Example Tx Data Path Filter Implementation

ADC

JESD204B

RECEIVER

HALF-BAND

FILTER 3

RECEIVER FIR

(DECIMATION

1, 2, 4)

QEC

FILTER

CORRECTION

DIGITAL

GAIN

DEC5

RECEIVER

HALF-BAND

FILTER 2

RECEIVER

HALF-BAND

FILTER 1

Figure 231. Data Rx Data Path Filter Implementation

AD9375BBCZ Datasheet(PDF) 58 Page - Analog Devices

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