AD9375BBCZ datasheet(60/61 Pages) AD

60 / 61 page

AD9375

Data Sheet

Rev. 0 | Page 60 of 61

JTAG BOUNDARY SCAN

The AD9375 provides support for a JTAG boundary scan. Five

dual-function pins are associated with the JTAG interface.

These pins, listed in Table 11, are used to access the on-chip test

access port. To enable the JTAG functionality, set the GPIO_0

through GPIO_3 pins according to Table 12 depending on how the

desired JESD204B sync pin (that is, SYNCINB0+, SYNCINB0−,

SYNCINB1+, SYNCINB1−, SYNCOUTB0+, or SYNCOUTB0−)

is configured in the software (LVDS or CMOS mode). Pull the

TEST pin high to enable the JTAG mode.

Table 11. Dual-Function Boundary Scan Test Pins

Mnemonic

JTAG Mnemonic

Description

GPIO_4

TRST

Test access port reset

GPIO_5

TDO

Test data output

GPIO_6

TDI

Test data input

GPIO_7

TMS

Test access port mode select

GPIO_18

TCK

Test clock

Table 12. JTAG Modes

Test Pin Level

GPIO_0 to GPIO_3

Description

XXXX1

Normal operation

1001

JTAG mode with LVDS

JESD204B sync signals

1011

JTAG mode with CMOS

JESD204B sync signals

1 X means don’t care.

AD9375BBCZ Datasheet(PDF) 60 Page - Analog Devices

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