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ISO1640BDR Datasheet(PDF) 6 Page - Texas Instruments

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Part # ISO1640BDR
Description  ISO164x Hot-Swappable Bidirectional I2C Isolators with Enhanced EMC and GPIOs
PDF  46 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ISO1640BDR Datasheet(HTML) 6 Page - Texas Instruments

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
UNIT
Supply Voltage
VCC1, VCC2
–0.5
6
V
Input/Output Voltage
SDA1, SCL1
–0.5
VCCX + 0.5(3)
V
SDA2, SCL2
–0.5
VCCX + 0.5(3)
INx (ISO1644 only)
-0.5
VCCX + 0.5
Input/Output Current
SDA1, SCL1
0
20
mA
SDA2, SCL2
0
100
IIO (ISO1644 only)
-15
15
Temperature
Maximum junction temperature, TJ
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2)
All voltage values are with respect to the local ground pin (GND1 or GND2) and are peak voltage values.
(3)
During powered off hotswap, the I2C bus pins can be 0 V < SDAx, SCLx < 6 V. Maximum voltage for INx must not exceed 6 V.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic
discharge
Human body model (HBM), per ANSI/
ESDA/JEDEC JS-001(1)
All pins
±6000
V
ISO1640/1: Bus pins (SDA1, SCL1)
±10000
V
ISO1640/1: Bus pins (SDA2, SCL2)
±14000
V
ISO1644: Bus pins (SDA1, SCL1)
±8000
V
ISO1644: Bus pins (SDA2, SCL2)
±8000
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±1500
V
Contact discharge per IEC 61000-4-2; Isolation barrier withstand test(3) (4)
±8000
V
Same side unpowered IEC ESD
contact discharge per IEC 61000-4-2;
Side 2
ISO1640/1: SCL2, SDA2
±8000
V
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3)
IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
(4)
Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VCC1(UVLO+)
UVLO threshold when supply voltage is rising on Side 1
2.7
2.9
V
VCC1(UVLO-)
UVLO threshold when supply voltage is falling on Side 1
2.3
2.6
V
VCC2(UVLO+)
UVLO threshold when supply voltage is rising on Side 2
2
2.25
V
VCC2(UVLO-)
UVLO threshold when supply voltage is falling on Side 2
1.7
1.8
V
VHYS1(UVLO)
Supply voltage UVLO hysteresis, Side 1
100
150
mV
VHYS2(UVLO)
Supply voltage UVLO hysteresis, Side 2
100
150
mV
VCC1
Supply voltage, Side 1
3.0
5.5
V
VCC2
Supply voltage, Side 2
2.25
5.5
V
VSDA1,
VSCL1
I2C Input and output signal voltages, Side 1
0
VCC1
V
ISO1640, ISO1641, ISO1644
SLLSFC2C – MAY 2021 – REVISED JUNE 2021
www.ti.com
6
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: ISO1640 ISO1641 ISO1644



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