ISO1640BDR datasheet(27/46 Pages) TI

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C-out

40 mV

50 mV

SDA1

OL1

IHT1

ILT1

PU1

node

CC1

SDA1

GND1

PU2

bus

CC2

SDA2

GND2

VREF

ISO164x

Figure 8-4. SDA Channel Design and Voltage Levels at SDA1

At first sight, the arrangement of the internal buffers suggests a closed signal loop that is prone to latch-up.

However, this loop is broken by implementing an output buffer (B) whose output low-level is raised by a diode

drop to approximately 0.65 V, and the input buffer (C) that consists of a comparator with defined hysteresis.

The comparator’s upper and lower input thresholds then distinguish between the proper low-potential of 0.4 V

(maximum) driven directly by SDA1 and the buffered output low-level of B.

Figure 8-5 demonstrate the switching behavior of the I2C isolator, ISO164x, between a master node at SDA1

and a heavy loaded bus at SDA2.

OL1

IHT1

SDA1

SDA2

SDA1

Transmit

Delay

Transmit

Delay

Receive

Delay

IHT2

50%

30%

Receive

Delay

Receive

Delay

VCC1

VCC2

VCC1

VCC2

OL1

Figure 8-5. SDA Channel Timing in Receive and Transmit Directions

8.5.1 Receive Direction (Left Diagram of Figure 8-5)

When the I2C bus drives SDA2 low, SDA1 follows after a certain delay in the receive path. The output low is the

buffered output of VOL1 = 0.65 V, which is sufficiently low to be detected by Schmitt-trigger inputs with a minimum

input-low voltage of VIL = 0.9 V at 3 V supply levels.

When SDA2 is released, its voltage potential increases towards VCC2 following the time-constant formed

by RPU2 and Cbus. After the receive delay, SDA1 is released and also rises towards VCC1, following the

time-constant RPU1 × Cnode. Because of the significant lower time-constant, SDA1 may reach VCC1 before

SDA2 reaches VCC2 potential.

8.5.2 Transmit Direction (Right Diagram of Figure 8-5)

When a master drives SDA1 low, SDA2 follows after a certain delay in the transmit direction. When SDA2 turns

low it also causes the output of buffer B to turn low but at a higher 0.65 V level. This level cannot be observed

immediately as it is overwritten by the lower low-level of the master.

However, when the master releases SDA1, the voltage potential increases and first must pass the upper input

threshold of the comparator, VIHT1, to release SDA2. SDA1 then increases further until it reaches the buffered

output level of VOL1 = 0.65 V, maintained by the receive path. When comparator C turns high, SDA2 is released

after the delay in transmit direction. It takes another receive delay until B’s output turns high and fully releases

SDA1 to move toward VCC1 potential.

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ISO1640, ISO1641, ISO1644

SLLSFC2C – MAY 2021 – REVISED JUNE 2021

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