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ISO1640BDR Datasheet(PDF) 15 Page - Texas Instruments |
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ISO1640BDR Datasheet(HTML) 15 Page - Texas Instruments |
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15 / 46 page ![]() 6.12 I2C Switching Characteristics over recommended operating conditions, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.25 V ≤ VCC2 ≤ 2.75 V, 3 V ≤ VCC1 ≤ 3.6 V tf2 Output signal fall time (SDA2 and SCL2) 0.7 × VCC2 ≥ VO ≥ 0.3 × VCC2, R2 = 72 Ω, C2 = 400 pF, see Test Diagram 16 26.5 40 ns 0.9 × VCC2 ≥ VO ≥ 400 mV, R2 = 72Ω, C2 = 400 pF, see Test Diagram 38 53.3 78 tpLH1-2 Low-to-high propagation delay, side 1 to side 2 VI = 535 mV, VO = 0.7 × VCC2, R1 = 953 Ω, R2 = 72 Ω, C1 and C2 = 10 pF, VCC1 = 3.3 V, see Test Diagram 20 30 ns tpHL1-2 High-to-low propagation delay, side 1 to side 2 VI = 550 mV, VO = 0.3 × VCC2, R1 = 953 Ω, R2 = 72 Ω, C1 and C2 = 10 pF, VCC1 = 3.3 V, see Test Diagram 80 130 ns tpLH2-1 Low-to-high propagation delay, side 2 to side 1(1) VI = 0.4 x VCC2, VO = 0.7 x VCC1, R1 = 953 Ω, R2 = 72 Ω, C1 and C2 = 10 pF, VCC1 = 3.3 V, see Test Diagram 40 48 ns tpHL2-1 High-to-low propagation delay, side 2 to side 1(1) VI = 0.4 x VCC2, VO = 0.3 × VCC1, R1 = 953 Ω, R2 = 72 Ω, C1 and C2 = 10 pF, VCC1 = 3.3 V, see Test Diagram 70 100 ns PWD1-2 Pulse width distortion |tpHL1-2 – tpLH1-2| R1 = 953 Ω, R2 = 72 Ω, C1 and C2 = 10 pF, VCC1 = 3.3 V see Test Diagram 60 104 ns PWD2-1 Pulse width distortion(1) |tpHL2-1 – tpLH2-1| R1 = 953 Ω, R2 = 72 Ω, C1 and C2 = 10 pF, VCC1 = 3.3 V see Test Diagram 25 55 ns tLOOP1 Round-trip propagation delay on side 1(1) 0.4 V ≤ VI ≤ 0.3 × VCC1, R1 = 953 Ω, C1 = 40 pF, R2 = 72 Ω, C2 = 400 pF, see Test Diagram 62 74 ns 3 V ≤ VCC1, VCC2 ≤ 3.6 V tf1 Output signal fall time (SDA1 and SCL1) 0.7 × VCC1 ≥ VO ≥ 0.3 × VCC1, R1 = 953 Ω, C1 = 40 pF, R2 = 95.3 Ω, C2 = 400 pF, see Test Diagram 8 17 29 ns 0.9 × VCC1 ≥ VO ≥ 900 mV, R1 = 953 Ω, C1 = 40 pF, see Test Diagram 15 25 48 tf2 Output signal fall time (SDA2 and SCL2) 0.7 × VCC2 ≥ VO ≥ 0.3 × VCC2, R2 = 95.3 Ω, C2 = 400 pF, see Test Diagram 14 23 47 ns 0.9 × VCC2 ≥ VO ≥ 400 mV, R2 = 95.3 Ω, C2 = 400 pF, see Test Diagram 30 50 100 tpLH1-2 Low-to-high propagation delay, side 1 to side 2 VI = 535 mV, VO = 0.7 × VCC2, R1 = 953 Ω, R2 = 95.3 Ω, C1 and C2 = 10 pF, see Test Diagram 21 29 ns tpHL1-2 High-to-low propagation delay, side 1 to side 2 VI = 550 mV, VO = 0.3 × VCC2, R1 = 953 Ω, R2 = 95.3 Ω, C1 and C2 = 10 pF, see Test Diagram 59 88 ns tpLH2-1 Low-to-high propagation delay, side 2 to side 1(1) VI = 0.4 x VCC2, VO = 0.7 x VCC1, R1 = 953 Ω, R2 = 95.3 Ω, C1 and C2 = 10 pF, see Test Diagram 40 47 ns tpHL2-1 High-to-low propagation delay, side 2 to side 1(1) VI = 0.4 x VCC2, VO = 0.3 × VCC1, R1 = 953 Ω, R2 = 95.3 Ω, C1 and C2 = 10 pF, see Test Diagram 70 100 ns PWD1-2 Pulse width distortion |tpHL1-2 – tpLH1-2| R1 = 953 Ω, R2 = 95.3 Ω, C1 and C2 = 10 pF, see Test Diagram 39 61 ns PWD2-1 Pulse width distortion(1) |tpHL2-1 – tpLH2-1| R1 = 953 Ω, R2 = 95.3 Ω, C1 and C2 = 10 pF, see Test Diagram 25 48 ns tLOOP1 Round-trip propagation delay on side 1(1) 0.4 V ≤ VI ≤ 0.3 × VCC1, R1 = 953 Ω, C1 = 40 pF, R2 = 95.3 Ω, C2 = 400 pF, see Test Diagram 65 78 ns www.ti.com ISO1640, ISO1641, ISO1644 SLLSFC2C – MAY 2021 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: ISO1640 ISO1641 ISO1644 |
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