PCM1820 datasheet(32/120 Pages) TI

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8.3.6.3 Programmable Channel Phase Calibration

In addition to the gain calibration, the phase delay in each channel can be finely calibrated or adjusted in steps

of one modulator clock cycle for a cycle range of 0 to 255 for the phase error of the analog microphone. The

modulator clock, which is the same clock used for ADC_MOD_CLK, is 6.144 MHz (the output data sample rate

is multiples or submultiples of 48 kHz) or 5.6448 MHz (the output data sample rate is multiples or submultiples

of 44.1 kHz). For the digital microphone interface, the phase calibration clock is dependent on the PDM clock

used. For a PDM_CLK of 6.144 MHz (the output data sample rate is multiples or submultiples of 48 kHz) or

5.6448 MHz (the output data sample rate is multiples or submultiples of 44.1 kHz), the phase calibration clock

is the same as PDM_CLK. For a PDM_CLK equal to or lower than 3.072 MHz (the output data sample rate is

multiples or submultiples of 48 kHz), the phase calibration clock used is 3.072 MHz. Similarly, for a PDM_CLK of

2.8224 MHz, 1.4112 MHz, or 705.6 kHz (the output data sample rate is multiples or submultiples of 44.1 kHz),

and the phase calibration clock used is 2.8224 MHz. This feature is very useful for applications that must match

the phase with fine resolution between each channel, including any phase mismatch across channels resulting

from external components or microphones. Table 8-16 shows the available programmable options for channel

phase calibration for the analog or digital microphone with a PDM_CLK of 6.144 MHz or 5.6448 MHz.

Table 8-16. Channel Phase Calibration Programmable Settings

P0_R64_D[7:0] : CH1_PCAL[7:0]

CHANNEL PHASE CALIBRATION SETTING FOR INPUT CHANNEL 1

0000 0000 = 0d (default)

Input channel 1 phase calibration with no delay

0000 0001 = 1d

Input channel 1 phase calibration delay is set to one cycle of the modulator clock

0000 0010 = 2d

Input channel 1 phase calibration delay is set to two cycles of the modulator clock

…

1111 1110 = 254d

Input channel 1 phase calibration delay is set to 254 cycles of the modulator clock

1111 1111 = 255d

Input channel 1 phase calibration delay is set to 255 cycles of the modulator clock

For a digital microphone interface with a PDM_CLK frequency below 3.072 MHz, the phase calibration range

is from 0 to 127 of the phase calibration clock (3.072 MHz for the output data sample rate is multiples or

submultiples of 48 kHz and 2.8224 MHz for the output data sample rate is multiples or submultiples of 44.1 kHz).

This range can be configured using CH1_PCAL[7:1] for channel 1.

Similarly, the channel phase calibration setting for input channel 2 to channel 4 can be configured using the

CH2_PCAL (P0_R69) to CH4_PCAL (P0_R79) register bits, respectively.

The phase calibration feature must not be used when the analog input and PDM input are used together for

simultaneous conversion.

8.3.6.4 Programmable Digital High-Pass Filter

To remove the DC offset component and attenuate the undesired low-frequency noise content in the record data,

the device supports a programmable high-pass filter (HPF). The HPF is not a channel-independent filter setting

but is globally applicable for all ADC channels. This HPF is constructed using the first-order infinite impulse

response (IIR) filter, and is efficient enough to filter out possible DC components of the signal. Table 8-17 shows

the predefined –3-dB cutoff frequencies available that can be set by using the HPF_SEL[1:0] register bits of

P0_R107. Additionally, to achieve a custom –3-dB cutoff frequency for a specific application, the device also

allows the first-order IIR filter coefficients to be programmed when the HPF_SEL[1:0] register bits are set to

2'b00. Figure 8-17 shows a frequency response plot for the HPF filter.

Table 8-17. HPF Programmable Settings

P0_R107_D[1:0] :

HPF_SEL[1:0]

-3-dB CUTOFF FREQUENCY

SETTING

-3-dB CUTOFF FREQUENCY AT

16-kHz SAMPLE RATE

-3-dB CUTOFF FREQUENCY AT

48-kHz SAMPLE RATE

Programmable 1st-order IIR filter

01 (default)

0.00025 × fS

4 Hz

12 Hz

0.002 × fS

32 Hz

96 Hz

0.008 × fS

128 Hz

384 Hz

TLV320ADC3120

SBASA91A – DECEMBER 2020 – REVISED JUNE 2021

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