PCM1820 datasheet(21/120 Pages) TI

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th Sample

(n+1)

th Sample

FSYNC

BCLK

SDOUT

N-1

N-2

N-3

N-1

N-2

N-3

N-1

N-2

Slot-0

(Word Length : N)

Slot-1

(Word Length : N)

Slot-2 to Slot-7

(Word Length : N)

N-1

Slot-0

(Word Length : N)

TX_OFFSET = 2

Figure 8-3. TDM Mode Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 2)

N-1

N-2

N-3

N-1

N-2

N-3

N-1

N-2

N-3

Slot-0

(Word Length : N)

Slot-1

(Word Length : N)

Slot-2 to Slot-7

(Word Length : N)

N-1

N-2

N-3

Slot-0

(Word Length : N)

FSYNC

BCLK

SDOUT

th Sample

(n+1)

th Sample

Figure 8-4. TDM Mode Protocol Timing (TX_OFFSET = 0 and BCLK_POL = 1)

For proper operation of the audio bus in TDM mode, the number of bit clocks per frame must be greater than

or equal to the number of active output channels times the programmed word length of the output channel data.

The device supports FSYNC as a pulse with a 1-cycle-wide bit clock, but also supports multiples as well. For a

higher BCLK frequency operation, using TDM mode with a TX_OFFSET value higher than 0 is recommended.

8.3.1.2.2 Inter IC Sound (I2S) Interface

The standard I2S protocol is defined for only two channels: left and right. The device extends the same protocol

timing for multichannel operation. In I2S mode, the MSB of the left slot 0 is transmitted on the falling edge of

BCLK in the second cycle after the falling edge of FSYNC. Immediately after the left slot 0 data transmission, the

remaining left slot data are transmitted in order. The MSB of the right slot 0 is transmitted on the falling edge of

BCLK in the second cycle after the rising edge of FSYNC. Immediately after the right slot 0 data transmission,

the remaining right slot data are transmitted in order. FSYNC and each data bit is transmitted on the falling edge

of BCLK. Figure 8-5 to Figure 8-8 illustrate the protocol timing for I2S operation with various configurations.

N-1

N-2

N-1

N-2

Left

Slot-0

(Word Length : N)

Left

Slot-2 to Slot-3

(Word Length : N)

N-1

N-2

FSYNC

BCLK

SDOUT

th Sample

(n+1)

th Sample

N-1

N-2

Right

Slot-0

(Word Length : N)

Right

Slot-2 to Slot-3

(Word Length : N)

Left

Slot-0

(Word Length : N)

Figure 8-5. I2S Mode Standard Protocol Timing (TX_OFFSET = 0)

N-1

N-2

Left

Slot-0

(Word Length : N)

Left

Slot-2 to Slot-3

(Word Length : N)

N-1

FSYNC

BCLK

SDOUT

th Sample

(n+1)

th Sample

N-1

Right

Slot-0

(Word Length : N)

Right

Slot-2 to Slot-3

(Word Length : N)

Left

Slot-0

(Word Length : N)

TX_OFFSET = 1

Figure 8-6. I2S Protocol Timing (TX_OFFSET = 1)

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TLV320ADC3120

SBASA91A – DECEMBER 2020 – REVISED JUNE 2021

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PCM1820 Datasheet(PDF) 21 Page - Texas Instruments

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