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PCM1820 Datasheet(PDF) 69 Page - Texas Instruments |
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PCM1820 Datasheet(HTML) 69 Page - Texas Instruments |
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69 / 120 page  Table 8-65. MST_CFG1 Register Field Descriptions Bit Field Type Reset Description 7-4 FS_RATE[3:0] R/W 0100b Programmed sample rate of the ASI bus (not used when the device is configured in slave mode auto clock configuration). 0d = 7.35 kHz or 8 kHz 1d = 14.7 kHz or 16 kHz 2d = 22.05 kHz or 24 kHz 3d = 29.4 kHz or 32 kHz 4d = 44.1 kHz or 48 kHz 5d = 88.2 kHz or 96 kHz 6d = 176.4 kHz or 192 kHz 7d = 352.8 kHz or 384 kHz 8d = 705.6 kHz or 768 kHz 9d to 15d = Reserved; Don't use 3-0 FS_BCLK_RATIO[3:0] R/W 1000b Programmed BCLK to FSYNC frequency ratio of the ASI bus (not used when the device is configured in slave mode auto clock configuration). 0d = Ratio of 16 1d = Ratio of 24 2d = Ratio of 32 3d = Ratio of 48 4d = Ratio of 64 5d = Ratio of 96 6d = Ratio of 128 7d = Ratio of 192 8d = Ratio of 256 9d = Ratio of 384 10d = Ratio of 512 11d = Ratio of 1024 12d = Ratio of 2048 13d to 15d = Reserved; Don't use 8.6.2.15 ASI_STS Register (Address = 0x15) [Reset = 0xFF] ASI_STS is shown in Figure 8-85 and described in Table 8-66. Return to the Table 8-51. This register s the ASI bus clock monitor status register Figure 8-85. ASI_STS Register 7 6 5 4 3 2 1 0 FS_RATE_STS[3:0] FS_RATIO_STS[3:0] R-1111b R-1111b Table 8-66. ASI_STS Register Field Descriptions Bit Field Type Reset Description 7-4 FS_RATE_STS[3:0] R 1111b Detected sample rate of the ASI bus. 0d = 7.35 kHz or 8 kHz 1d = 14.7 kHz or 16 kHz 2d = 22.05 kHz or 24 kHz 3d = 29.4 kHz or 32 kHz 4d = 44.1 kHz or 48 kHz 5d = 88.2 kHz or 96 kHz 6d = 176.4 kHz or 192 kHz 7d = 352.8 kHz or 384 kHz 8d = 705.6 kHz or 768 kHz 9d to 14d = Reserved status 15d = Invalid sample rate www.ti.com TLV320ADC3120 SBASA91A – DECEMBER 2020 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 69 Product Folder Links: TLV320ADC3120 |
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