PCM1820 datasheet(9/120 Pages) TI

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7.5 Electrical Characteristics (continued)

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS,

TDM slave mode, and PLL on (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIH(GPIx)

High-level digital input logic

voltage threshold

IN2P_GPI1 and MICBIAS_GPI2 digital pins, AVDD 1.8-V

operation

0.65 × AVDD

AVDD + 0.3

IN2P_GPI1 and MICBIAS_GPI2 digital pins, AVDD 3.3-V

operation

AVDD + 0.3

VOL(GPOx)

Low-level digital output

voltage

IN2M_GPO2 digital pin, IOL = –2 mA, AVDD 1.8-V

operation

0.45

IN2M_GPO2 digital pin, IOL = –2 mA, AVDD 3.3-V

operation

0.4

VOH(GPOx)

High-level digital output

voltage

IN2M_GPO2 digital pin, IOH = 2 mA, AVDD 1.8-V

operation

AVDD – 0.45

IN2M_GPO2 digital pin, IOH = 2 mA, AVDD 3.3-V

operation

2.4

IIH(GPIx)

Input logic-high leakage for

digital inputs

IN2P_GPI1 and MICBIAS_GPI2 digital pins, input =

AVDD

–5

0.1

µA

IIL(GPIx)

Input logic-high leakage for

digital inputs

IN2P_GPI1 and MICBIAS_GPI2 digital pins, input = 0 V

–5

0.1

µA

CIN

Input capacitance for digital

inputs

All digital pins

RPD

Pulldown resistance for

digital I/O pins when

asserted on

kΩ

TYPICAL SUPPLY CURRENT CONSUMPTION

IAVDD

Current consumption in

sleep mode (software

shutdown mode)

All external clocks stopped, AVDD = 3.3 V, internal

AREG

µA

IAVDD

All external clocks stopped, AVDD = 1.8 V, external

AREG supply (AREG shorted to AVDD)

IIOVDD

All external clocks stopped, IOVDD = 3.3 V

0.5

IIOVDD

All external clocks stopped, IOVDD = 1.8 V

0.5

IAVDD

Current consumption with

ADC 2-channel operating

at fS 48-kHz, PLL off

and BCLK = 512 × fS

AVDD = 3.3 V, internal AREG

11.1

IAVDD

AVDD = 1.8 V, external AREG supply (AREG shorted to

AVDD)

10.5

IIOVDD

IOVDD = 3.3 V

0.1

IIOVDD

IOVDD = 1.8 V

0.05

IAVDD

Current consumption with

ADC 2-channel operating

at fS 16-kHz, PLL on and

BCLK = 256 × fS

AVDD = 3.3 V, internal AREG

11.3

IAVDD

AVDD = 1.8 V, external AREG supply (AREG shorted to

AVDD)

10.6

IIOVDD

IOVDD = 3.3 V

0.05

IIOVDD

IOVDD = 1.8 V

0.02

IAVDD

Current consumption with

ADC 2-channel operating

at fS 48-kHz, PLL on

and BCLK = 256 × fS

AVDD = 3.3 V, internal AREG

12.2

IAVDD

AVDD = 1.8 V, external AREG supply (AREG shorted to

AVDD)

11.6

IIOVDD

IOVDD = 3.3 V

0.1

IIOVDD

IOVDD = 1.8 V

0.05

(1)

Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured

A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.

(2)

All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may

result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter

removes out-of-band noise, which, although not audible, may affect dynamic specification values.

(3)

For best distortion performance, use input AC-coupling capacitors with low-voltage coefficient.

(4)

Gain drift = gain variation (in temperature range) / typical gain value (gain at room temperature) / temperature range × 106 measured

with gain in linear scale.

(5)

Phase drift = phase deviation (in temperature range) / (temperature range).

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TLV320ADC3120

SBASA91A – DECEMBER 2020 – REVISED JUNE 2021

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