LTC6948 datasheet(25/32 Pages) AD

25 / 32 page

LTC5594

Rev A

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data is transferred to the internal register at the falling

edge of the 16th clock cycle (parallel load).

Multiple Byte Transfers

More efficient data transfer of multiple bytes is accom-

plished by using the LTC5594’s register address auto-

increment feature as shown in the timing diagram. The

serial port master sends the destination register address

in the first byte and reads or writes data in the second

byte as before, but on the third byte the address pointer

is auto-incremented by 1 and the serial port master can

read or write to subsequent registers. If the register ad-

dress pointer attempts to increment past 23 (0x17), it is

automatically reset to 0.

SDO_MODE Control Bit

The SDO output has two modes of operation as shown

in the timing diagram. When register 0x16 control bit

SDO_MODE = 0, the SDO pin functions as a normal output

which is Hi-Z during a write command. If SDO_MODE = 1,

the SDO output is put into a serial repeater mode where

SDO echos the command written to SDI before readback

of register contents either in read or write mode. This

can be used in high bus noise environments where it is

necessary to perform error checking on commands sent

to the serial port.

A simplified schematic of the SDO output is shown in

Figure 18. The OVDD supply sets the logic level of the

output, and a 25Ω series resistor limits the output current.

APPLICATIONS INFORMATION

the chip that the VCC supply be brought up first before the

OVDD supply. This is to prevent the ESD diode connected

between OVDD and VCC from getting damaged.

Figure 18. Simplified Schematic of the SDO Pin Interface

SERIAL PORT

The SPI compatible serial port provides control and moni-

toring functionality.

Communication Sequence

The serial bus is comprised of CSB, SCK, SDI and SDO.

Data transfers to the part are accomplished by the

serial bus master device first taking CSB low to enable the

LTC5594’s port. Input data applied on SDI is clocked on

the rising edge of SCK, with all transfers MSB first. The

communicationburstisterminatedbytheserialbusmaster

returning CSB high. See the timing diagrams for details.

Data is read from the part during a communication burst

using SDO. Readback may be multidrop (more than one

LTC5594 or other serial device connected in parallel on

the serial bus), as SDO is high impedance (Hi-Z) when

CSB = 1.

Single Byte Transfers

The serial port is arranged as a simple memory map, with

status and control available in 23 registers as shown in

the appendix. All data bursts are comprised of at least two

8-bit bytes. The most significant bit of the first byte is the

read/write bit. Setting this bit to 1 puts the serial port into

read mode. The next 7 bits of the first byte are address bits

and can be set from 0x00 to 0x17. The subsequent byte,

or bytes, is data from/to the specified register address.

See the timing diagrams for details. Note that the written

LTC5594

GND

OVDD

SDO

5594 F18

VCC

Figure 17. Simplified Schematic of the OVDD Pin Interface

LTC5594

GND

OVDD

DIGITAL

INPUTS

SDO

5594 F17

VCC

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