LTC5594

26

Rev A

For more information www.analog.com

APPLICATIONS INFORMATION

Register Defaults

The register map and defaults are given in Tables 9 and

10 in the Appendix. When the device is powered up, the

registers may not be reset to their default values. By

writing a 1 to the SRST bit (bit[3]) of register 0x16, the

device will go into soft reset and the registers will be reset

to their default values.

Impairment Minimization

The LTC5594 contains circuitry for minimizing receiver

impairments such as DC offset, phase and gain error,

and nonlinearity. An example block diagram of a receiver

application is shown in Figure 19. A 2-tone source signal

is applied to the RF input and the I and Q ADC outputs are

measured in the digital domain to determine the optimized

register settings in the LTC5594 for minimization of the

impairments.

Figure 20 shows the nonoptimized baseband spectrum

and Figure 21 shows the optimized baseband spectrum

for a 2-tone test signal at 5.8GHz.

Figure 19. Example Block Diagram of a Receiver with 2-Tone Test Signal for Impairment Minimization

ADC

ADC

LTC5594

RF

0º

90º

SPI

LINEARITY

DC OFFSET

IMAGE

ADJUST

AD9208

ADF5355

I

Q

DSP

MEASUREMENT

AND OPTIMIZATION

2-TONE

SIGNAL

SOURCE

5594 F19