DS20006554A datasheet(25/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

command (see Table 3), the upper byte of the register address, and the lower byte of the register address. The bus

master then does an I2C read. During each acknowledge (A) bit the device fetches data from the read address and

then increments the read address. The device then transmits the data to the bus master during the next 8 SCL cycles.

The bus master terminates the read with a not-acknowledge (NA) followed by a STOP condition (P). See Figure 9.

After the I2C write there can be unlimited idle time on the bus before the I2C read, but the device cannot tolerate other

I2C bus traffic between the I2C write and the I2C read. Care must be taken to ensure that the I2C read is the first

command on the bus after the I2C write to ensure the two-part read transaction happens correctly.

an I2C write to the device. The first three bytes of this transaction are the SPI Write command (see Table 3), the

upper byte of the register address, and the lower byte of the register address. Subsequent bytes are data bytes to

be written. After each data byte is received, the device writes the byte to the write address and then increments the

write address. The bus master terminates the write with a STOP condition (P). See Figure 10.

EEPROM Writes (ZL30261 and ZL30263 Only). The EEPROM memory is accessible when the EESEL bit is 1. The

bus master first does an I2C write to transmit the SPI Write Enable command (see Table 3) to the device. The bus

master then does an I2C write to transmit data to the device as described in the Register Write Transactions

paragraph above. See Figure 11.

EEPROM Read Status (ZL30261 and ZL30263 Only). The bus master first does an I2C write to transmit the SPI

Read Status command (see Table 3) to the device. The bus master then does an I2C read to get the status byte. In

this byte, the least significant bit is set to 1 if the transfer is still in progress and 0 if the transfer has completed. See

Figure 12. Similar to read transactions described above, the I2C write and the I2C read cannot be separated by other

I2C bus traffic.

I2C Features Not Supported by the Device. The I2C specification has several optional features that are not

supported by the device. These are: 3.4Mbit/s high-speed mode (Hs-mode), 10-bit device addressing, general call

address, software reset, and device ID. The device does not hold SCL low to force the master to wait.

I2C Slave Address. By default the upper 5

bits of the device’s 7-bit slave address are fixed at 11101 and the lower

2 bits can be pin-configured for any of three values as shown in the table in section 5.2. For a device that can auto-

configure from EEPROM at power-up, its I2C slave address can be set to any value during auto-configuration at

power-up by writing the the I2CA register as part of the configuration script.

Bit Order. The I2C specification requires device address, register address and all data bytes to be transmitted most

significant bit first on the SDA signal.

Note: as required by the I2C specification, when power is removed from the device, the SDA and SCL pins are left

floating so they don’t obstruct the bus lines.

Figure 9 - I2C Read Transaction Functional Timing

slave device

address

R/W A

7 bits

read

command

0 (write)

slave device

address

S = START condition

P = STOP condition

A = acknowledge (SDA low)

NA = not acknowledge (SDA high)

R/W A

7 bits

data byte1

data byteN NA P

1 (read)

reg. address

upper byte

reg. address

lower byte

DS20006554A Datasheet(PDF) 25 Page - Microchip Technology

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