DS20006554A datasheet(15/94 Pages) MICROCHIP

15 / 94 page

ZL30260-ZL30263

Data Sheet

DS20006554A

When a fractional scaling scenario involves multiplying an integer M times multiple scaling ratios N1 / D1 through

Nn / Dn, the equations above can still be used if the numerators are multiplied together to get N = N1 x N2

x … x Nn

and the denominators are multiplied together to get D = D1 x D2

x … x Dn.

The easiest way to calculate the exact values to write to the APLL registers is to use the ZL3026x evaluation software,

available on the Microchip website. This software can be used even when no evaluation board is attached to the

computer.

Note: After the APLL's feedback divider settings are configured in register fields AFBDIV, AFBREM, AFBDEN and

AFBBP, the APLL enable bit PLLEN.APLLEN should be changed from 0 to 1 to cause the APLL to reacquire lock

with the new settings. The real-time lock/unlock status of the APLL is indicated by APLLSR.ALK.

5.5.5

Fractional Output Divider

As shown in Figure 1 and Figure 5, the APLL has a fractional output divider. This allows the APLL to be the source

of two unrelated frequency families, one from the integer divider, and one from the fractional divider.

Configuration of the fractional output divider is very similar to configuration of the APLL’s feedback divider. The

fractional divider is enabled by setting ACR1.ENFDIV. Internally, the exact divider value is expressed in the form

FDIV + FREM / FDEN * 2-(36-FBP). The input clock to the fractional divider is APLL VCO frequency divided by 2 (fVCO/2).

The FDIV term is a fixed-point number with 4 integer bits and a configurable number of fractional bits (up to 36, as

specified by FBP). Typically FBP is set to 12 to specify that FDIV has 36

– 12 = 24 fractional bits.

The output clock from the fractional divider has good phase noise on rising edges but worse phase noise on falling

edges and can have non-50% duty cycle. Applications that only use clock rising edges

can use the fractional divider’s

output clock directly. For applications that care about 50% duty cycle and/or the phase noise of both rising edges

and falling edges, the fractional divider should be followed by an even medium-speed divider value (2, 4, 6

, 8…).

The low-speed divider can be used to further divide the output clock if needed.

The maximum output frequency for the fractional divider is fVCO/10. This means the minimum fractional divider value

is 5.0. Including the need for a divide-by-2 in the medium-speed divider, the maximum frequency for a 50% duty-

cycle output clock signal is fVCO/20. The minimum output frequency for the fractional divider is fVCO/32 since the

internal FDIV value has 4 integer bits. The combination FDIV=0, FREM=0, FDEN=1 specifies to divide by 16.0. The

medium-speed and low-speed dividers can be configured to follow the fractional output divider to create output

frequencies down to <1Hz.

The following equations show how to calculate the register values for the situation where the fractional divider should

divide by the integer M and the ratio of integers N / D. In other words,

frac_div_output_freq = (VCO_freq / 2) / (M * N / D)

An example of this is starting with VCO_freq = 3750MHz (to get low-

jitter Ethernet frequencies through the APLL’s

integer divider) and using the APLL’s fractional divider to get 155.52MHz for SONET/SDH applications. In this

example, M=12, N=15625, D=15552 are appropriate values to get 155.52MHz.

fdiv = trunc(M * N / D * 224)

(1)

lsb_fraction = M * N / D * 224

– fdiv

(2)

FDEN = D

(3)

FREM = round(lsb_fraction * FDEN)

(4)

FBP = 36

– 24 = 12

(5)

FDIV[39:0] = fdiv * 2FBP

(6)

The trunc() function returns only the integer portion of the number. The round() function rounds the number to the

nearest integer. In Equation (1),

the temporary variable ‘fdiv’ is the full-precision feedback divider value, M * N / D,

truncated after the 24th fractional bit. In Equation (2) the temporary variable 'lsb_fraction' is the fraction that was

truncated in Equation (1) and therefore is not represented in the fdiv value. In Equation (3), FDEN is set to the

denominator of the original M * N / D ratio. In Equation (4), FREM is calculated as the integer numerator of a fraction

(with denominator FDEN) that equals the 'lsb_fraction' temporary variable. In Equation (5) FBP is set to 36

– 24 =12

DS20006554A Datasheet(PDF) 15 Page - Microchip Technology

DS20006554A Datasheet(HTML) 15 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

Datasheet Download

Link URL