| Electronic Components Datasheet Search |
|
DS20006554A Datasheet(PDF) 37 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
DS20006554A Datasheet(HTML) 37 Page - Microchip Technology |
|
37 / 94 page ![]() ZL30260-ZL30263 Data Sheet 37 © 2021 Microchip Technology Inc. DS20006554A Register Name: PLLEN Register Description: APLL Enable Register Register Address: 03h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name — — — — — — — APLLEN Default 0 0 0 0 0 0 0 0 Bit 0: APLL Enable (APLLEN). This bit enables or disables the APLL. See section 5.5.4. 0 = Disabled 1 = Enabled Register Name: ICEN Register Description: Input Clock Enable Register Register Address: 04h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name — — — — — IC3EN IC2EN IC1EN Default 0 0 0 0 0 0 0 0 Bit 2: Input Clock 3 Enable (IC3EN). This bit enables and disables the input clock 3 differential receiver and input dividers. See section 5.4. 0 = Disabled 1 = Enabled Bit 1: Input Clock 2 Enable (IC2EN). This bit enables and disables the input clock 2 differential receiver and input dividers. See section 5.4. 0 = Disabled 1 = Enabled Bit 0: Input Clock 1 Enable (IC1EN). This bit enables and disables the input clock 1 differential receiver and input dividers. See section 5.4. 0 = Disabled 1 = Enabled |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |