LTM4664 datasheet(42/138 Pages) AD

42 / 138 page

LTM4664A

Rev. 0

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pin enabled will detect the presence of the external

clock and disable its output.

Multiple channels need to tie all the VOSNS+_Cn pins

together, and all the VOSNS–_Cn pins together, COMP_na

and COMP_nb pins together as well. Do not assert bit[4]

of MFR_CONFIG_ALL except in a PolyPhase application.

The user must share the SYNC, SHARE_CLK, FAULT_Cn,

and ALERT pins of these parts. Be sure to use pull-up

resistors on SYNC, FAULT_Cn, SHARE_CLK and ALERT.

EXTERNAL/INTERNAL TEMPERATURE SENSE

Temperature is measured using the internal diode-connected

PNP transistors on either of the TSNS_C0b or TSNS_C1b

pins corresponding to channel 0 or 1. TSNS_Cnb pins

should be connected to their respective TSNS_Cna pins,

and these returns are directly connected to the LTM4664A

PSM SGND_C0_C1 pin. Two different currents are applied to

the diode (nominally 2µA and 32µA) and the temperature is

calculated from a ΔVBE measurement made with the internal

16-bit monitor ADC (see Figure 2, Block Diagram).

The LTM4664A PSM channels will only implement ΔVBE

temperature sensing, therefore MFR_PWM_MODE bit[5]

is reserved.

RCONFIG (RESISTOR CONFIGURATION) PINS

There are six input pins utilizing 1% resistors for these pins

to select key operating parameters. The pins are ASEL,

FSWPH_CFG, VOUTC0_CFG, VOUTC1_CFG, VTRIMC0_

CFG, VTRIMC1_CFG. If pins are floated, the value stored in

the corresponding NVM command is used. If bit 6 of the

MFR_CONFIG_ALL configuration command is asserted in

NVM, the resistor input is ignored upon power-up except

for ASEL which is always respected. The resistor config-

uration pins are only measured during a power-up reset

or after a MFR_RESET or after a RESTORE_USER_ALL

command is executed.

The VOUTn_CFG pin settings are described in Table 1.

These pins set the LTM4664A VOUTC0 and VOUTC1 output

voltage coarse settings. If the pin is open, the VOUT_

COMMAND command is loaded from NVM to determine

the output voltage. The default setting is to have the

switcher off unless the voltage configuration pins are

installed. The VTRIMn_CFG pins in Table 2 are used to set

the output voltage fine adjustment setting. Both combine

to offer several distinct output voltages.

The following parameters are set as a percentage of the

output voltage if the RCONFIG pins are used to determine

the output voltage:

VOUT_OV_FAULT_LIMIT....................................+10%

VOUT_OV_WARN_LIMIT....................................+7.5%

VOUT_MAX.........................................................+7.5%

VOUT_MARGIN_HIGH........................................+5%

VOUT_MARGIN_LOW.........................................–5%

VOUT_UV_FAULT_LIMIT....................................–7%

The FSWPH_CFG pin settings are described in Table 3.

This pin selects the switching frequency and phase of each

channel. The phase relationships between the two channels

and SYNC pin are determined in Table 3. To synchronize

to an external clock, the part should be put into external

clock mode (SYNC output disabled but frequency set to the

nominal value). If no external clock is supplied, the part will

clock at the programmed frequency. If the application is

multiphase and the SYNC signal between chips is lost, the

parts will not operate at the designed phase even if they are

programmed and trimmed to the same frequency.

This may increase the ripple voltage on the output, pos-

sibly produce undesirable operation. If the external SYNC

signal is being generated internally and external SYNC is

not selected, bit 10 of MFR_PADS will be asserted. If no

frequency is selected and the external SYNC frequency

is not present, a PLL_FAULT will occur. If the user does

not wish to see the ALERT from a PLL_FAULT even if

there is not a valid synchronization signal at power-up,

the ALERT mask for PLL_FAULT must be written. See

the description on SMBALERT_MASK for more details.

If the SYNC pin is connected between multiple ICs only

one of the ICs should have the SYNC pin enabled using

the MFR_CONFIG_ALL[4] =1, and all other ICs should

be configured to have the SYNC pin disabled with MFR_

CONFIG_ALL[4] =0.

The ASEL pin settings are described in Table 4. ASEL

selects slave address for the LTM4664A PSM. For more

detail, refer to Table 5.

DUAL 25A/30A PSM OPERATION

LTM4664 Datasheet(PDF) 42 Page - Analog Devices

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