LTM4664 datasheet(22/138 Pages) AD

22 / 138 page

LTM4664A

Rev. 0

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PIN FUNCTIONS

to configure the LTM4664A’s Channel 0 output to pow-

er-up to a VOUT_COMMAND value (and associated output

voltage monitoring and protection/fault-detection thresh-

olds) different from those of NVM contents. (See the 4:1

Divider Application Information section.) Minimize capac-

itance especially when the pin is left open to assure accu-

rate detection of the pin state. Note that use of RCONFIGs

on VOUTC0_CFG/VTRIMC0_CFG can affect the VOUTC0

range setting (MFR_PWM_MODE0 [1]) and loop gain.

VOUTC1_CFG (J7): Output Voltage Select Pin for VOUTC1,

Coarse Setting. If the VOUTC1_CFG and VTRIMC1_CFG

pins are both left open or, if the LTM4664A is config-

ured to ignore pin-strap (RCONFIG) resistors, i.e., MFR_

CONFIG_ALL [6] = 1b then the LTM4664A’s target VOUTC1

output voltage setting (VOUT_COMMAND1) and associ-

ated OV/UV warning and fault thresholds are dictated at

SVIN power up according to the LTM4664A’s NVM con-

tents, in precisely the same fashion that the VOUTC1_CFG

and VTRIMC1_CFG pins affect the respective settings of

VOUT1/Channel 1. (See VOUTC1_CFG, VTRIMC1_CFG and

the 4:1 Divider Application Information section.) Minimize

capacitance—especially when the pin is left open—to

assure accurate detection of the pin state. Note that use

of RCONFIGs on VOUTC1_CFG/VTRIMC1_CFG can affect

the VOUTC1 range setting (MFR_PWM_MODE1 [1]) and

loop gain. A resistor divider from VDD25 to SGND_C0_C1.

See page 43.

ASEL (J8): Serial Bus Address Configuration Pin. On any

given I2C/SMBus serial bus segment, every device

must have its own unique slave address. If this pin is

left open, the LTM4664A powers up to a slave address

set by MFR_ADDRESS[6:0] (see Table 4). The facto-

ry-default setting is 0x4F (hexadecimal), i.e., 1001111b

(industry standard convention is used throughout this

document: 7-bit slave addressing). The lower four bits of

the LTM4664A’s slave address can be altered from the

NVM-set value by connecting a resistor from this pin to

SGND. Minimize capacitance—especially when the pin is

left open—to assure accurate detection of the pin state.

See 4:1 Divider Application Information section.

RUN_C0, RUN_C1 (J9, K8 Respectively): Enable Run

Input for Channels 0 and 1, respectively. Open-drain input

and output. Logic high on these pins enables the respective

outputs of the LTM4664A. These open-drain output pins

hold the pin low until the LTM4664A is out of reset and

VIN3_C1 is detected to exceed VIN_ON. A pull-up resis-

tor to 3.3V is required in the application. The LTM4664A

pulls RUN_C0 and/or RUN_C1 low, as appropriate, when

a global fault and/or channel-specific fault occurs whose

fault response is configured to latch off and cease reg-

ulation; issuing a CLEAR_FAULTS command via I2C or

power cycling SVIN is necessary to restart the module, in

such cases. Do not pull RUN logic high with a low imped-

ance source. Use PGOODS2 and FAULTS2 to sequence on

RUN_C0, and RUN_C1 for the dual 25A/30A stage.

ALERT (J10): Open-Drain Digital Output. A pull-up

resistor to 3.3V is required in the application only if

SMBALERT interrupt detection is implemented in one’s

SMBus system.

VTRIMC0_CFG (K5): Output Voltage Select Pin for VOUTC0,

Fine Setting. Works in combination with VOUTC0_CFG

to affect the VOUT_COMMAND (and associated output

voltage monitoring and protection/fault-detection thresh-

olds) of Channel 0, at SVIN power-up. (See VOUTC0_CFG

and the Dual 25A/30A PSM Applications Information sec-

tion.) Minimize capacitance especially when the pin is left

open to assure accurate detection of the pin state. Note

that use of RCONFIGs on VOUTC0_CFG/VTRIMC0_CFG

can affect the VOUTC0 range setting (MFR_PWM_MODE0

[1]) and loop gain.

VDD25 (K6): Internally Generated 2.5V Power Supply

Output Pin. Do not load this pin with external current;

it is used strictly to bias internal logic and provides cur-

rent for the internal pull-up resistors connected to the

configuration-programming pins. No external decoupling

is required.

WP (K7): Write Protect Pin, Active High. An internal 10μA

current source pulls this pin to VDD33. If WP is open cir-

cuit or logic high, only I2C writes to PAGE, OPERATION,

CLEAR_FAULTS, MFR_CLEAR_PEAKS and MFR_EE_

UNLOCK are supported. Additionally, Individual faults

can be cleared by writing 1b’s to bits of interest in reg-

isters prefixed with “STATUS”. If WP is low, I2C writes

are unrestricted.

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