ISO1640 datasheet(22/45 Pages) TI

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8 Detailed Description

8.1 Overview

The I2C bus consists of a two-wire communication bus that supports bidirectional data transfer between a master

device and several slave devices. The master, or processor, controls the bus, specifically the serial clock (SCL)

line. Data is transferred between the master and slave through a serial data (SDA) line. This data can be

transferred in four speeds: standard mode (0 to 100 kbps), fast mode (0 to 400 kbps), fast-mode plus (0 to 1

Mbps), and high-speed mode (0 to 3.4 Mbps).

The I2C bus operates in bidirectional, half-duplex mode, using open collector outputs to allow for multiple

devices to share the bus. When a specific device is ready to communicate on the bus, it can take control pulling

the lines low accordingly in order to transmit data. A standard digital isolator or optocoupler is designed to

transfer data in a single direction. In order to support an I2C bus, external circuitry is required to separate the

bidirectional bus into two unidirectional signal paths. The ISO164x-Q1 devices internally handle the separation

and partitioning of the transmit and receive signals, integrating the external circuitry needed and provide

the open-collector signals. They provide high electromagnetic immunity and low emissions at low power

consumption. Each isolation channel has a logic input and output buffer separated by TI's double capacitive

silicon dioxide (SiO2) insulation barrier. When used in conjunction with isolated power supplies, these devices

block high voltages, isolate grounds, and prevent noise currents from entering the local ground and interfering

with or damaging sensitive circuitry.

8.2 Functional Block Diagrams

SDA2

SCL1

SCL2

GND2

GND1

VCC2

VCC1

SDA1

VREF

Figure 8-1. ISO1640-Q1 Block Diagram

8.3 Isolation Technology Overview

The ISO164x family of devices has an ON-OFF keying (OOK) modulation scheme to transmit the digital data

across a silicon dioxide based isolation barrier. The transmitter sends a high frequency carrier across the barrier

to represent one digital state and sends no signal to represent the other digital state. The receiver demodulates

the signal after advanced signal conditioning and produces the output through a buffer stage. These devices

also incorporate advanced circuit techniques to maximize the CMTI performance and minimize the radiated

emissions due the high frequency carrier and switching.

ISO1640-Q1

SLLSFC3A – MARCH 2020 – REVISED DECEMBER 2021

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ISO1640 Datasheet(PDF) 22 Page - Texas Instruments