ISO1640 datasheet(27/45 Pages) TI

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SDA

SCL

START

Condition

STOP

condition

7-bit

ADDRESS

8-bit

DATA

8-bit

DATA

R/W

ACK /

NACK

ACK

Figure 9-2. Timing Diagram of a Complete Data Transfer

The master initiates a transaction by creating a START condition, following by the 7-bit address of the slave

it wishes to communicate with. This is followed by a single read and write (R/W) bit, representing whether the

master wishes to write to (0), or to read from (1) the slave. The master then releases the SDA line to allow the

slave to acknowledge the receipt of data.

The slave responds with an acknowledge bit (ACK) by pulling the SDA pin low during the entire high time of the

9th clock pulse on the SCL signal, after which the master continues in either transmit or receive mode (according

to the R/W bit sent), while the slave continues in the complementary mode (receive or transmit, respectively).

The address and the 8-bit data bytes are sent most significant bit (MSB) first. The START bit is indicated by

a high-to-low transition of SDA while SCL is high. The STOP condition is created by a low-to-high transition of

SDA while SCL is high.

If the master writes to a slave, it repeatedly sends a byte with the slave sending an ACK bit. In this case, the

master is in master-transmit mode and the slave is in slave-receive mode.

If the master reads from a slave, it repeatedly receives a byte from the slave, while acknowledging (ACK) the

receipt of every byte but the last one (see Figure 9-3). In this situation, the master is in master-receive mode and

the slave is in slave-transmit mode.

The master ends the transmission with a STOP bit, or may send another START bit to maintain bus control for

further transfers.

From Master to Slave

From Slave to Master

S Slave Address

R A

DATA

A P

S Slave Address

W A

DATA

A P

Master Transmitter writing to Slave Receiver

Master Receiver reading from Slave Transmitter

A = acknowledge

A = not acknowledge

S = Start

P = Stop

R = Read

W = Write

Figure 9-3. Transmit or Receive Mode Changes During a Data Transfer

When writing to a slave, a master mainly operates in transmit-mode and only changes to receive-mode when

receiving acknowledgment from the slave.

When reading from a slave, the master starts in transmit-mode and then changes to receive-mode after sending

a READ request (R/W bit = 1) to the slave. The slave continues in the complementary mode until the end of a

transaction.

Note

The master ends a reading sequence by not acknowledging (NACK) the last byte received. This

procedure resets the slave state machine and allows the master to send the STOP command.

9.2 Typical Application

Figure 9-4 shows isolated I2C data acquisition system built with TI microcontroller, analog-to-digital converter,

and I2C isolator, ISO164x-Q1.

www.ti.com

ISO1640-Q1

SLLSFC3A – MARCH 2020 – REVISED DECEMBER 2021

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ISO1640 Datasheet(PDF) 27 Page - Texas Instruments

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