ISO1640 datasheet(28/45 Pages) TI

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The entire circuit operates from a single 3.3-V supply. A low-power push-pull converter, SN6501-Q1, drives a

center-tapped transformer with an output that is rectified and linearly regulated to provide a stable 5-V supply for

the data converters.

0.1 F

10 F

MBR0520L

1:2.2

0.1 F

SN6501-Q1

GND

3.3 V

GND

OUT

6,7

13,14

TPS76750-Q1

10 F

5VISO

ISO Barrier

Vcc

VCC1

GND1

SDA1

ISO164x-Q1

0.1 F

10 F

TMS320F28035PAGQ

VDD

VSS

SDA

SCL

SCL1

VCC2

GND2

SDA2

SCL2

0.1 F

ADS1115-Q1

SDA

SCL

AIN0

AIN3

1.5 k

VDD

ADDR

GND

0.1 F

5VISO

4 Analog

Inputs

Figure 9-4. Isolated I2C Data Acquisition System

Figure 9-5. Isolated I2C and SPI Data Acquisition System

9.2.1 Design Requirements

The recommended power supply voltages must be from 3 V to 5.5 V for VCC1 and 2.25 V to 5.5 V for VCC2. A

recommended decoupling capacitor with a value of 0.1 µF is required between both the VCC1 and GND1 pins,

and the VCC2 and GND2 pins to support of power supply voltage transients and to ensure reliable operation at

all data rates.

9.2.2 Detailed Design Procedure

Although the ISO1640-Q1 features bidirectional data channels, the device performs optimally when side 1

(SDA1 and SCL1) is connected to a single controller or node of an I2C network while side 2 (SDA2 and SCL2)

is connected to the I2C bus. The maximum load permissible on the input lines, SDA1 and SCL1, is ≤ 80 pF and

on the output lines, SDA2 and SCL2, is ≤ 400 pF. In addition to the bidirectional data and clock channels for the

I2C network, the ISO1644 includes 3 GPIOs which can be used for static I/O lines or for a 3 wire SPI interface.

These lines are designed to support up to 50 Mbps data transfer rate.

The power-supply capacitor with a value of 0.1-µF must be placed as close to the power supply pins as possible.

The recommended placement of the capacitors must be 2-mm maximum from input and output power supply

pins (VCC1 and VCC2).

The minimum pullup resistors on the input lines, SDA1 and SCL1 to VCC1 must be selected in such a way that

input current drawn is ≤ 3.5 mA. The minimum pullup resistors on the input lines, SDA2 and SCL2, to VCC2

must be selected in such a way that output current drawn is ≤ 50 mA. The maximum pullup resistors on the

bus lines (SDA1 and SCL1) to VCC1 and on bus lines (SDA2 and SCL2) to VCC2, depends on the load and

ISO1640-Q1

SLLSFC3A – MARCH 2020 – REVISED DECEMBER 2021

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