MAX694CSLASHD datasheet(6/18 Pages) MAXIM

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Typical Applications

MAX691, MAX693, and MAX695

A typical connection for the MAX691/693/695 is shown

in Figure 1. CMOS RAM is powered from VOUT. VOUT is

internally connected to VCC when 5V power is present,

or to VBATT when VCC is less than the battery voltage.

VOUT can supply 50mA from VCC, but if more current

is required, an external PNP transistor can be added.

When VCC is higher than VBATT, the BATT ON output

goes low, providing 25mA of base drive for the external

transistor. When VCC is lower than VBATT, an internal

200Ω MOSFET connects the backup battery to VOUT.

The quiescent current in the battery backup mode is 1µA

maximum when VCC is between 0V and VBATT–700mV.

Reset Output

A voltage detector monitors VCC and generates a RESET

output to hold the microprocessor’s Reset line low when

VCC is below 4.65V (4.4V for MAX693). An internal

monostable holds RESET low for 50ms* after VCC rises

above 4.65V (4.4V for MAX693). This prevents repeated

toggling of RESET even if the 5V power drops out and

recovers with each power line cycle.

The crystal oscillator normally used to generate the clock

for microprocessors takes several milliseconds to start.

Since most microprocessors need several clock cycles

to reset, RESET must be held low until the micropro-

cessor clock oscillator has started. The MAX690 family

power-up RESET pulse lasts 50ms* to allow for this

oscillator start-up time. The manual reset switch and

the 0.1µF capacitor connected to the reset bus can be

omitted if manual reset is not needed. An inverted, active

high, RESET output is also supplied.

Power-Fail Detector

The MAX691/93/95 issues a nonmaskable interrupt (NMI)

to the microprocessor when a power failure occurs. The

+5V power line is monitored via two external resistors

connected to the power-fail input (PFI). When the volt-

age at PFI falls below 1.3V, the power-fail output (PFO)

drives the processor’s NMI input low. If a power-fail

threshold of 4.8V is chosen, the microprocessor will

have the time when VCC fails from 4.8V to 4.65V to save

data into RAM. An earlier power-fail warning can be

generated if the unregulated DC input of the 5V regulator

is available for monitoring.

RAM Write Protection

The MAX691/MAX693/MAX695 CE OUT line drives the

Chip Select inputs of the CMOS RAM. CE OUT follows

CE IN as long as VCC is above the 4.65V (4.4V for

MAX693) reset threshold. If VCC falls below the reset

threshold, CE OUT goes high, independent of the logic

level at CE IN. This prevents the microprocessor from

writing erroneous data into RAM during power-up, power-

down, brownouts, and momentary power interruptions.

The LOW LINE output goes low when VCC falls below

4.65V (4.4V for MAX693).

*200ms for MAX695

Figure 1. MAX691/693/695 Typical Application

+5V

VCC

INPUT

NO CONNECTION

0.1µF

VCC

VBATT

I/O

NMI

RESET

PFI

GND

BATT ON

LOW LINE

WDO

SYSTEM STATUS INDICATORS

BATTERY

MAX691

MAX693

MAX695

OSC IN

VOUT

CE IN

CE OUT

PFO

WDI

RESET

OSC SEL

AUDIBLE

ALARM

ADDRESS

DECODE

CMOS

RAM

MICROPROCESSOR

OTHER SYSTEM RESET SOURCES

A0-A15

MAX690–MAX695

Microprocessor Supervisory Circuits

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