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MMPF0100 Datasheet(PDF) 65 Page - NXP Semiconductors |
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MMPF0100 Datasheet(HTML) 65 Page - NXP Semiconductors |
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65 / 137 page ![]() NXP Semiconductors 65 PF0100 FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Table 69. Register SW3AOFF - ADDR 0x3E Name Bit # R/W Default Description SW3AOFF 5:0 R/W 0x00 Sets the SW3A output voltage (independent) or SW3A/B output voltage (Single/Dual phase), during Sleep mode. See Table 65 for all possible configurations. SW3AOFF 6 R 0x00 Sets the operating output voltage range for SW3A (independent) or SW3A/B (single/dual phase) on sleep mode. This bit inherits the value configured on bit SW3A[6] during OTP or TBB configuration. See Table 65 for all possible configurations. UNUSED 7 – 0x00 unused Table 70. Register SW3AMODE - ADDR 0x3F Name Bit # R/W Default Description SW3AMODE 3:0 R/W 0x08 Sets the SW3A (independent) or SW3A/B (single/ dual phase) switching operation mode. See Table 30 for all possible configurations. UNUSED 4 – 0x00 unused SW3AOMODE 5 R/W 0x00 Set status of SW3A (independent) or SW3A/B (single/dual phase) when in sleep mode. • 0 = OFF • 1 = PFM UNUSED 7:6 – 0x00 unused Table 71. Register SW3ACONF - ADDR 0x40 Name Bit # R/W Default Description SW3AILIM 0 R/W 0x00 SW3A current limit level selection • 0 = High level current limit • 1 = Low level current limit UNUSED 1 R/W 0x00 unused SW3AFREQ 3:2 R/W 0x00 SW3A switching frequency selector. See Table 38. SW3APHASE 5:4 R/W 0x00 SW3A phase clock selection. See Table 36. SW3ADVSSPEED 7:6 R/W 0x00 SW3A DVS speed selection. See Table 35. Table 72. Register SW3BVOLT - ADDR 0x43 Name Bit # R/W Default Description SW3B 5:0 R/W 0x00 Sets the SW3B output voltage (independent) during normal operation mode. See Table 65 for all possible configurations. SW3B 6 R 0x00 Sets the operating output voltage range for SW3B (independent). Set during OTP or TBB configuration only. See Table 65 for all possible configurations. UNUSED 7 – 0x00 unused |
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