MMPF0100 datasheet(83/137 Pages) NXP

83 / 137 page

NXP Semiconductors

PF0100

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

Table 96. Register VGEN2CTL - ADDR 0x6D

Name

Bit #

R/W

Default

Description

VGEN2

3:0

R/W

0x80

Sets VGEN2 output voltage.

See Table 92 for all possible configurations.

VGEN2EN

–

0x00

Enables or disables VGEN2 output

• 0 = OFF

• 1 = ON

VGEN2STBY

R/W

0x00

Set VGEN2 output state when in standby. Refer

to Table 94.

VGEN2LPWR

R/W

0x00

Enable low-power mode for VGEN2. Refer to

Table 94.

UNUSED

–

0x00

unused

Table 97. Register VGEN3CTL - ADDR 0x6E

Name

Bit #

R/W

Default

Description

VGEN3

3:0

R/W

0x80

Sets VGEN3 output voltage.

See Table 93 for all possible configurations.

VGEN3EN

–

0x00

Enables or disables VGEN3 output

• 0 = OFF

• 1 = ON

VGEN3STBY

R/W

0x00

Set VGEN3 output state when in standby. Refer

to Table 94.

VGEN3LPWR

R/W

0x00

Enable low-power mode for VGEN3. Refer to

Table 94.

UNUSED

–

0x00

unused

Table 98. Register VGEN4CTL - ADDR 0x6F

Name

Bit #

R/W

Default

Description

VGEN4

3:0

R/W

0x80

Sets VGEN4 output voltage.

See Table 93 for all possible configurations.

VGEN4EN

–

0x00

Enables or disables VGEN4 output

• 0 = OFF

• 1 = ON

VGEN4STBY

R/W

0x00

Set VGEN4 output state when in standby. Refer

to Table 94.

VGEN4LPWR

R/W

0x00

Enable low-power mode for VGEN4. Refer to

Table 94.

UNUSED

–

0x00

unused

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