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MMPF0100 Datasheet(PDF) 80 Page - NXP Semiconductors

Part # MMPF0100
Description  14 channel configurable power management integrated circuit
PDF  137 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MMPF0100 Datasheet(HTML) 80 Page - NXP Semiconductors

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NXP Semiconductors
PF0100
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.6
LDO regulators description
This section describes the LDO regulators provided by the PF0100. All regulators use the main bandgap as reference. Refer to 6.3 Bias
and references block description, page 24 for further information on the internal reference voltages.
A low-power mode is automatically activated by reducing bias currents when the load current is less than I_Lmax/5. However, the lowest
bias currents may be attained by forcing the part into its low-power mode by setting the VGENxLPWR bit. The use of this bit is only
recommended when the load is expected to be less than I_Lmax/50, otherwise performance may be degraded.
When a regulator is disabled, the output is discharged by an internal pull-down. The pull-down is also activated when RESETBMCU is low.
Figure 30. General LDO block diagram
6.4.6.1
Transient response waveforms
Idealized stimulus and response waveforms for transient line and transient load tests are depicted in Figure 31. Note that the transient line
and load response refers to the overshoot, or undershoot only, excluding the DC shift.
Figure 31. Transient waveforms
VGENx
VINx
VINx
VGENx
CGENx
VGENxEN
VGENxLPWR
VREF
VGENx
I
2C
Interface
Discharge
+
_
10 us
10 us
VINx
Transient Line Stimulus
VINx_INITIAL
VINx_FINAL
1.0 us
1.0 us
IMAX/10
IMAX
ILOAD
Transient Load Stimulus
Undershoot
IL = IMAX/10
VOUT
VOUT Transient Load Response
IL = IMAX
Overshoot
Undershoot
VOUT
VOUT Transient Line Response
Overshoot
VINx_INITIAL
VINx_FINAL



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