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MPC8540 Datasheet(PDF) 632 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 632 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
14-6
Freescale Semiconductor
Three-Speed Ethernet Controllers
layers and additional information must be added to the LLC in order to provide information
regarding those protocols. Protocols that fall into this category include IP and IPX. The method
used to provide this additional protocol information is called a subnetwork access protocol
(SNAP) frame. A SNAP encapsulation is indicated by the DSAP and SSAP addresses being set to
0xAA and the LLC control field being set to 0x03. If that address is seen, a SNAP header follows.
The SNAP header is five bytes long. The first three bytes consist of the organization code (SNAP
OUI), which is assigned by the IEEE. The last two bytes become the type value set from the
original Ethernet specifications if SNAP OUI = 0, or they become a SNAP protocol identifier if
SNAP OUI is non zero.
The three-speed Ethernet controller (TSEC) allows the flexibility to accelerate the identification
and retrieval of all the standard and non-standard protocols mentioned above. Figure 14-5 shows
the block diagram of the TSEC.
Figure 14-5. TSEC Block Diagram
Address/Data
filtering
MAC Layer
DMA
Tx system CLK
data path
Pack
words
Unpack
words
Rx FIFO
2 Kbytes
FIFO
control
Tx FIFO
2 Kbytes
Tx/Rx descriptors
Tx/Rx data
Tx/Rx status
Block
interface
Clocks
To PHY
To PHY
To PHY
To PHY
GMII
Reduced
Signal
Reduced
Signal
TBI
TBI
GMII
RGMI
RTBI
TBI
or
or
or
MII Mgmt
MIB
Counters
Interface
Interface



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