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MPC8540 Datasheet(PDF) 633 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 633 Page - Freescale Semiconductor, Inc |
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633 / 1302 page  Features MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 14-7 14.1.1 Three-Speed Ethernet Controller Overview The TSEC is designed to support 10, 100, and 1000 Mbps Ethernet/802.3 networks and contains the following components: • Ethernet media access controller (MAC) • First-in first-out (FIFO) controller • Direct memory access (DMA) controller • Ten-bit interface (TBI) • Register-based statistical module that supports management information base (MIB) remote monitoring (RMON) The most-significant byte of data in a receive or transmit data buffer corresponds to the most-significant byte of a frame, respectively. The complete TSEC is designed for single MAC applications. The TSEC supports several standard MAC-PHY interfaces to connect to an external Ethernet transceiver: • MII interface running at 10/100 Mbps • GMII interface running at 1 Gbps • TBI interface that can be connected to a SerDes device for fibre channel applications. • Reduced signal count versions of the GMII (RGMII) and ten-bit (RTBI) interfaces While most of this document refers to the non-reduced signal count interfaces, it must be understood that these references also apply to the reduced signal count interfaces. The TSEC software programming model is similar to the MPC8260 (PowerQUICC II) device. Hence, it enables Freescale customers to leverage already implemented Ethernet drivers, reducing the software development cycle. 14.2 Features The MPC8540 TSEC includes these distinctive features: • IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant • Support for different Ethernet physical interfaces: — 10/100/1Gb IEEE 802.3 GMII — 10/100 Mbps IEEE 802.3 MII — 10-Mbps IEEE 802.3 MII — 1-Gbps IEEE 802.3z TBI — 10/100 Mbps RMII — 1-Gbps full-duplex RGMII — 1-Gbps RTBI |
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