MPC8540 datasheet(637/1302 Pages) FREESCALE

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External Signal Descriptions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-11

EC_MDC

Management data clock. In GMII, MII, RGMII, RTBI or TBI mode this signal is a clock (typically

2.5 MHz) supplied by the MAC (IEEE–set minimum period of 400 ns or a frequency of 2.5 MHz,

but the device may be configured up to 12.5 MHz if supported by the PHY at that speed). This

clock is generated by dividing the core complex bus (CCB) clock by eight. The ratio can be

modified further by writing to MIIMCFG[29:31].

Note that this signal is used during reset to configure the TSEC interface to ‘reduced-signal’ or

‘non-reduced-signal’ mode. See Section 4.4.3, “Power-On Reset Configuration,” for more

information.

EC_MDIO

I/O Management data input/output, BIDI

State

Meaning

Asserted/Negated—In GMII, MII, RGMII, RTBI or TBI mode EC_MDIO is a

bidirectional signal to input PHY-supplied status during management read

cycles and output control during MII management write cycles.

Timing Asserted/Negated—This signal is required to be synchronous with the EC_MDC

signal.

TSECn_RX_CLK

Receive clock. In GMII, MII or RGMII mode, the receive clock TSECn_RX_CLK is a continuous

clock (2.5, 25, or 125 MHz) that provides a timing reference for TSECn_RX_DV, TSECn_RXD,

and TSECn_RX_ER.

In TBI mode, TSECn_RX_CLK is the input for a 62.5-MHz PMA receive clock, 0 split phase with

PMA_RX_CLK1 and is supplied by the SerDes.

In RTBI mode it is a 125-MHz receive clock.

TSECn_RX_DV

Receive data valid. In GMII or MII mode, if TSECn_RX_DV is asserted, the PHY is indicating

that valid data is present on the GMII and MII interfaces.

In RGMII mode, TSECn_RX_DV becomes RX_CTL. The RX_DV and RX_ERR are received on

this signal on the rising and falling edges of TSECn_RX_CLK.

In TBI mode, TSECn_RX_DV represents receive code group (RCG) bit 8. Together, with

RCG[9] and RCG[7:0], they represents the 10-bit encoded symbol of GMII receive signals.

In RTBI mode, TSECn_RX_DV represents receive code group (RCG) bit 4 and 9. On the

positive edge of the TSECn_RX_CLK, RCG[4] and RCG[3:0] represents the first half of the

10-bit encoded symbol. On the negative edge of the TSECn_RX_CLK, RCG[9] and RCG[8:4]

represents the second half of the 10-bit encoded symbol.

TSECn_RXD[7:0]

Receive data in. In GMII mode, TSECn_RXD[7:4] with TSECn_RXD[3:0], represent one

complete octet of data to be transferred from the PHY to the MAC when TSECn_RX_DV is

asserted.

In TBI mode, TSECn_RXD[7:4] represents RCG[7:4]. Together, with RCG[9:8] and RCG[3:0],

they represent the 10-bit encoded symbol of GMII receive signals.

In GMII mode, TSECn_RXD[3:0] represents a nibble of data to be transferred from the PHY to

the MAC when TSECn_RX_DV is asserted. A completely-formed SFD must be passed across

the MII. While TSECn_RX_DV is not asserted, TSECn_RXD has no meaning.

In RGMII or RTBI mode, TSECn_RXD[3:0] are received on the rising edge of TSECn_RX_CLK

and TSECn_RXD[7:4] are received on the falling edge of TSECn_RX_CLK.

In TBI mode, TSECn_RXD[3:0] represents RCG[3:0]. Together, with RCG[9:4], they represent

the 10-bit encoded symbol of GMII receive signals.

Table 14-1. TSEC Signals—Detailed Signal Descriptions (continued)

Signal

I/O

Description

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