MPC8540 datasheet(640/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-14

Freescale Semiconductor

Three-Speed Ethernet Controllers

14.5.2 Detailed Memory Map—Control/Status Registers

Table 14-3 lists the address, name, and a cross-reference to the complete description of each

at 0x2_4000 address offset and TSEC2 starts at 0x2_5000 address offset. The registers for TSEC1

are listed in Table 14-3, but the registers for TSEC2 are not. Note in Table 14-3 that the registers

are the same for TSEC2 except that the offset changes from 0x2_4nnn to 0x2_5nnn.

600–7FF

TSEC RMON MIB registers

800–8FF

TSEC HASH function registers

900–AFF

Reserved

B00–BFF

TSEC attribute registers

C00–FFF

Future expansion space

Table 14-3. Module Memory Map

Offset

Name

Access1

Reset

Section/Page

TSEC1 General Control and Status Registers

0x2_4000–

0x2_400C

Reserved

0x0000_0000

—

0x2_4010

IEVENT—Interrupt event register

R/W

0x0000_0000

14.5.3.1.1/14-20

0x2_4014

IMASK—Interrupt mask register

R/W

0x0000_0000

14.5.3.1.2/14-23

0x2_4018

EDIS—Error disabled register

R/W

0x0000_0000

14.5.3.1.3/14-24

0x2_401C

Reserved

0x0000_0000

—

0x2_4020

ECNTRL—Ethernet control register

R/W

0x0000_0000

14.5.3.1.4/14-25

0x2_4024

MINFLR—Minimum frame length register

R/W

0x0000_0040

14.5.3.1.5/14-26

0x2_4028

PTV—Pause time value register

R/W

0x0000_0000

14.5.3.1.6/14-27

0x2_402C

DMACTRL—DMA control register

R/W

0x0000_0000

14.5.3.1.7/14-28

0x2_4030

TBIPA—TBI PHY address register

R/W

0x0000_0000

14.5.3.1.8/14-29

0x2_4034–

0x2_4048

Reserved

0x0000_0000

—

TSEC1 FIFO Control and Status Registers

0x2_404C

FIFO_PAUSE_CTRL—FIFO pause control register

R/W

0x0000_0000

14.5.3.2.1/14-30

0x2_4050–

0x2_4088

Reserved

0x0000_0000

—

0x2_408C

FIFO_TX_THR—FIFO transmit threshold register

R/W

0x0000_0100

14.5.3.2.2/14-31

Table 14-2. Module Memory Map Summary (continued)

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