MPC8540 datasheet(636/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-10

Freescale Semiconductor

Three-Speed Ethernet Controllers

The TSEC network interface supports multiple options:

•

The MII option requires 18 I/O signals (including the EC_MDIO and EC_MDC MII

management interface) and supports both a data and a management interface to the PHY

(transceiver) device. The MII option supports both 10- and 100-Mbps Ethernet rates.

•

The GMII option is a superset of the MII signals and supports a 1-Gbps Ethernet rate.

•

The TBI interface shares signals with the GMII interface signals.

•

Finally, RGMII and RTBI options are reduced-signal implementations of the GMII and TBI

interfaces.

14.4.1 Detailed Signal Descriptions

Table 14-1 contains detailed descriptions of the TSEC interface signals. For RGMII mode details

please refer to the Hewlett-Packard reduced gigabit media-independent interface (RGMII)

specification version 1.2a, dated 9/22/2000. All other modes follow the IEEE 802.3 standard, 2000

Edition. Input signals not used are internally disabled. Output signals not used are driven low.

Table 14-1. TSEC Signals—Detailed Signal Descriptions

Signal

I/O

Description

TSECn_COL

Collision input. The behavior of this signal is not specified while in full-duplex mode.

State

Meaning

Asserted/Negated—In MII mode, this signal is asserted upon detection of a collision,

and must remain asserted while the collision persists.

This signal is not used in the TSEC GMII, TBI, RTBI and RGMII modes.

Timing Asserted/Negated—This signal is not required to transition synchronously with

TSECn_TX_CLK or TSECn_RX_CLK.

TSECn_CRS

Carrier sense input. In TBI and RTBI modes this signal can be used as SDET (signal detect),

an optional signal that some PHYs generate in TBI or RTBI modes. This signal is not used in

the TSEC GMII or RGMII modes.

State

Meaning

Asserted/Negated—In MII mode, TSECn_TX_CLK is asserted while the transmit or

receive medium is not idle. In the event of a collision, TSECn_CRS must

remain asserted for the duration of the collision.

Timing Asserted/Negated—This signal is not required to transition synchronously with

TSECn_TX_CLK or TSECn_RX_CLK.

TSECn_GTX_CLK

Gigabit transmit clock. This signal is an output from the TSEC into the PHY. In GMII, TBI, or

RTBI mode TSECn_GTX_CLK is a 125-MHz clock that provides a timing reference for TX_EN,

TXD, and TX_ER.

In RGMII mode TSECn_GTX_CLK becomes the transmit clock and provides timing reference

during 1000Base-T (125-MHz), 100Base-T (25-MHz) and 10Base-T (2.5-MHz) transmissions.

This signal is not used in MII mode.

EC_GTX_CLK125

Gigabit transmit 125-MHz source. This signal must be generated externally with a crystal or

oscillator, or is sometimes provided by the PHY. In GMII, RGMII, RTBI or TBI mode,

EC_GTX_CLK125 is a 125-MHz input into the TSEC and is used to generate all 125-MHz

related signals and clocks.

This input is not used in MII mode.

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