MPC8540 datasheet(634/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-8

Freescale Semiconductor

Three-Speed Ethernet Controllers

•

Full- and half-duplex support (1 Gbps supports only full-duplex)

•

IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or software

programmed PAUSE frame generation and recognition)

•

Support for out-of-sequence transmit queue (for initiating flow control)

•

Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and IEEE

802.1 virtual local area network (VLAN) frames

•

Retransmission from transmit FIFO following a collision

•

Support for CRC generation and verification of inbound/outbound packets

•

Address recognition

— Each exact match can be programmed to be accepted or rejected

— Broadcast address (accept/reject)

— Exact match 48-bit individual (unicast) address

— Hash (256-bit hash) check of individual (unicast) addresses

— Hash (256-bit hash) check of group (multicast) addresses

— Promiscuous mode

•

Extraction data and its associated buffer descriptors can be directed to the processor’s L2

cache to reduce access latency

•

Interrupt coalescing subject to a threshold frame counter and/or a threshold timer

(Independent functionality for received and transmitted frames)

•

RMON statistics support

14.3 Modes of Operation

The primary TSEC operational modes are the following:

•

Full- and half-duplex operation

This is determined by MACCFG2 register’s Full Duplex bit. Full-duplex mode is intended

for use on point to point links between switches or end node to switch. Half-duplex mode

is used in connections between an end node and a repeater or between repeaters.

If configured in half-duplex mode (only 10- and 100-Mbps operation; MACCFG2

method.

If configured in full-duplex mode (10/100/1Gb operation; MACCFG2 register’s Full

Duplex bit is set), the MAC supports flow control. If flow control is enabled, it allows the

MAC to receive or send PAUSE frames.

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