MPC8540 datasheet(635/1302 Pages) FREESCALE

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External Signal Descriptions

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-9

•

10- and 100-Mbps MII interface operation

The MAC-PHY interface operates in MII mode by configuring bits 22–23 of MACCFG2

(MACCFG2[I/F Mode] = 01). The MII is the media-independent interface defined by the

802.3 standard for 10/100 Mbps operation. The speed of operation is determined by the

TSECn_TX_CLK and TSECn_RX_CLK signals, which are driven by the transceiver. The

transceiver either auto-negotiates the speed or it may be controlled by software via the

serial management interface (EC_MDC/EC_MDIO signals) to the transceiver.

•

1-Gbps GMII and TBI interface operation

The MAC-PHY interface operates in GMII mode by configuring bits 22–23 of MACCFG2

(MACCFG2[I/F Mode] = 10). The GMII is the gigabit media-independent interface

defined by the 802.3 standard for 1-Gbps operation.

Independently, the MAC-PHY interface can also operate in TBI mode. Note that either the

TBI or GMII interface is chosen; not both at the same time. TBI is the ten-bit interface

which contains PCS functions (ten-bit encoding/decoding) as defined by the 802.3

standard.

In reduced signal count mode (RGMII or RTBI), the MAC remains configured in GMII or

TBI but the TSEC multiplexes and decodes the input signals and provides the MAC with

the expected interface.

TSEC provides the TSECn_GTX_CLK to the PHY in either GMII or TBI mode of

operation.

•

Address recognition options

The options supported are promiscuous, broadcast, exact individual address hash or exact

match, and multicast hash match. For detailed descriptions refer to Section 14.5.3.8.1,

“Individual Address Registers 0–7 (IADDRn),” Section 14.5.3.8.2, “Group Address

Registers 0–7 (GADDRn),” Section 14.5.3.4.1, “Receive Control Register (RCTRL),” and

Section 14.6.2.6, “Frame Recognition.”

•

RMON support

See Section 14.6.2.5, “RMON Support.”

•

Internal loop back

Internal loop back mode is selected through the Loop Back bit in the MACCFG1 register.

See Section 14.6.2.10, “Internal and External Loop Back,” for details.

14.4 External Signal Descriptions

This section defines the TSEC signals. The buses are described using the bus convention used in

IEEE 802.3 because the PHY follows this same convention (that is, TxD[7:0] means 0 is the lsb).

Notice that except for external physical interfaces the buses and registers follow a big-endian

format.

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