MPC8540 datasheet(638/1302 Pages) FREESCALE

638 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-12

Freescale Semiconductor

Three-Speed Ethernet Controllers

TSECn_RX_ER

Receive error

State

Meaning

Asserted/Negated—In GMII or MII mode, if TSECn_RX_ER and TSECn_RX_DV

are asserted, the PHY has detected an error in the current frame.

In TBI mode, TSECn_RX_ER represents RCG[9]. Together, with RCG[8:0],

they represent the 10-bit encoded symbol of GMII receive signals.

This signal is not used in the TSEC RTBI or RGMII modes.

TSECn_TX_CLK

Transmit clock in. In MII mode, TSECn_TX_CLK is a continuous clock (2.5 or 25 MHz) that

provides a timing reference for the TSECn_TX_EN, TSECn_TXD, and TSECn_TX_ER signals.

In GMII mode, TSECn_TX_CLK provides the 2.5 or 25-MHz timing reference during 10Base-T

and 100Base-T and comes from the PHY. In 1000Base-T this clock is not used and

TSECn_GTX_CLK (125 MHz) becomes the timing reference. The TSECn_GTX_CLK is

generated in the TSEC and provided to the PHY and the MAC. The TSECn_TX_CLK is

generated in the PHY and provided to the MAC.

In TBI mode, this signal is PMA receive clock 1 62.5 MHz, split phase with PMA_RX_CLK0, and

is supplied by the SerDes.

This signal is not used in the TSEC RTBI or RGMII modes.

TSECn_TXD[7:0]

Transmit data out. In GMII mode, TSECn_TXD[7:4], together with TSECn_TXD[3:0], represent

one complete octet of data to be sent from the MAC to the PHY when TSEC_TX_DV is asserted

and has no meaning while TSECn_TX_EN is negated.

In TBI mode, TSECn_TXD[7:4] represents transmit code group (TCG) bits 7:4. Together, with

TCG[9:8] and TCG[3:0], they represent the 10-bit encoded symbol.

In GMII or MII mode, TSECn_TXD[3:0] represent a nibble of data to be sent from the MAC to

the PHY when TSECn_TX_EN is asserted and have no meaning while TSECn_TX_EN is

negated.

In RGMII or RTBI mode, TSECn_TXD[3:0] are transmitted on the rising edge of

TSECn_TX_CLK, and TSECn_TXD[7:4] are transmitted on the falling edge of

TSECn_TX_CLK.

In TBI mode, TSECn_TXD[3:0] represents TCG[3:0]. Together, with TCG[9:4], they represent

the 10-bit encoded symbol.

Note that some of these signals are also used during reset to configure the TSEC interface in

GMII or TBI mode. Additionally, some of these signals are used for other reset configuration

settings for the MPC8540. See Section 4.4.3, “Power-On Reset Configuration,” for more

information.

TSECn_TX_EN

Transmit data valid. In GMII or MII mode, if TSECn_TX_EN is asserted, the MAC is indicating

that valid data is present on the GMII’s or the MII’s TSECn_TXD signals.

In RGMII mode, TSECn_TX_EN becomes TX_CTL. TX_EN and TX_ERR are asserted on this

signal on rising and falling edges of the TSECn_TX_CLK, respectively.

In TBI mode, TSECn_TX_EN represents TCG[8]. Together, with TCG[9] and TCG[7:0], they

represent the 10-bit encoded symbol.

In RTBI mode, TSECn_TX_EN represents TCG[4]. Together with TCG[9], TCG[3:0] and

TCG[8:5], they represent the 10-bit encoded symbol.

TSECn_TX_ER

Transmit error. In GMII or MII mode, assertion of TSECn_TX_ER for one or more clock cycles

while TSECn_TX_EN is asserted causes the PHY to transmit one or more illegal symbols.

Asserting TSECn_TX_ER has no effect while operating at 10 Mbps or while TSECn_TX_EN is

negated. This signal transitions synchronously with respect to TSECn_TX_CLK.

In TBI mode, TSECn_TX_ER represents TCG[9]. Together, with TCG[8:0], they represents the

10-bit encoded symbol.

This signal is not used in the TSEC RTBI or RGMII modes.

Table 14-1. TSEC Signals—Detailed Signal Descriptions (continued)

Signal

I/O

Description

MPC8540 Datasheet(PDF) 638 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 638 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL