MPC8540 datasheet(642/1302 Pages) FREESCALE

642 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-16

Freescale Semiconductor

Three-Speed Ethernet Controllers

0x2_4310

RXIC—Receive interrupt coalescing configuration

R/W

0x0000_0000

14.5.3.4.4/14-43

0x2_4314–

0x2_4320

Reserved

0x0000_0000

—

0x2_4324

CRBPTR—Current RxBD pointer register

0x0000_0000

14.5.3.4.5/14-44

0x2_4328–

0x2_433C

Reserved

0x0000_0000

—

0x2_4340

MRBLR—Maximum receive buffer length register

R/W

0x0000_0000

14.5.3.4.6/14-44

0x2_4344–

0x2_4380

Reserved

0x0000_0000

—

0x2_4384

RBPTR—RxBD pointer register

R/W

0x0000_0000

14.5.3.4.7/14-45

0x2_4388–

0x2_4400

Reserved

0x0000_0000

—

0x2_4404

RBASE—RxBD base address register

R/W

0x0000_0000

14.5.3.4.8/14-45

0x2_4408–

0x2_44FC

Reserved

0x0000_0000

—

TSEC1 MAC Registers

0x2_4500

MACCFG1—MAC configuration register 1

R/W

0x0000_0000

14.5.3.6.1/14-49

0x2_4504

MACCFG2—MAC configuration register 2

R/W

0x0000_7000

14.5.3.6.2/14-51

0x2_4508

IPGIFG—Inter-packet gap/inter-frame gap register

R/W

0x4060_5060

14.5.3.6.3/14-52

0x2_450C

HAFDUP—Half-duplex register

R/W

0x00A1_F037

14.5.3.6.4/14-53

0x2_4510

MAXFRM—Maximum frame length register

R/W

0x0000_0600

14.5.3.6.5/14-54

0x2_4514–

0x2_451C

Reserved

0x0000_0000

—

0x2_4520

MIIMCFG—MII management configuration register

R/W

0x0000_0000

14.5.3.6.6/14-54

0x2_4524

MIIMCOM—MII Management command register

R/W

0x0000_0000

14.5.3.6.7/14-55

0x2_4528

MIIMADD—MII Management address register

R/W

0x0000_0000

14.5.3.6.8/14-56

0x2_452C

MIIMCON—MII Management control register

0x0000_0000

14.5.3.6.9/14-57

0x2_4530

MIIMSTAT—MII Management status register

0x0000_0000

14.5.3.6.10/14-57

0x2_4534

MIIMIND—MII Management indicator register

0x0000_0000

14.5.3.6.11/14-58

0x2_4538

Reserved

0x0000_0000

—

0x2_453C

IFSTAT—Interface status register

R/W

0x0000_0000

14.5.3.6.12/14-58

0x2_4540

MACSTNADDR1—Station address register, part 1

R/W

0x0000_0000

14.5.3.6.13/14-59

Table 14-3. Module Memory Map (continued)

Offset

Name

Access1

Reset

Section/Page

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