MPC8540 datasheet(646/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-20

Freescale Semiconductor

Three-Speed Ethernet Controllers

14.5.3 Memory-Mapped Register Descriptions

This section provides a detailed description of all the TSEC registers. Because all of the TSEC

registers are 32 bits wide, only 32-bit register accesses are supported.

14.5.3.1 TSEC General Control and Status Registers

This section describes general control and status registers used for both transmitting and receiving

Ethernet frames. All of the registers are 32 bits wide.

14.5.3.1.1 Interrupt Event Register (IEVENT)

If an event occurs that sets a bit in the interrupt event (IEVENT) register, shown in Figure 14-6,

an interrupt is generated if the corresponding bit in the interrupt enable register (IMASK) is also

set. Clearing the IEVENT bit clears the interrupt signal. The bit in the IEVENT register is cleared

if a 1 is written to that bit position. A write of 0 has no effect.

These interrupts can be divided into operational interrupts, transceiver/network error interrupts,

and internal error interrupts. Interrupts that may occur in normal operation are:

•

GTSC, GRSC, TXF, TXB, TXC, RXF, RXB, RXC, and MSRO

Interrupts resulting from errors/problems detected in the network or transceiver are:

•

BABR, BABT, LC, and CRL/XDA

Interrupts resulting from internal errors are:

•

EBERR, XFUN, and BSY

Some of the error interrupts are independently counted in the management information base (MIB)

block counters. Software may choose to mask off these interrupts because these errors are visible

to network management through the MIB counters.

TSEC2 Registers

0x2_5000–

0x2_5FFC

TSEC2 registers2

1 R = means read-only, W = write only, R/W = read and write, LH = latches high, SC = self-clearing.

2 TSEC2 has the same memory-mapped registers that are described for TSEC1 from 0x 2_4000 to 0x2_4FFF except

the offsets are from 0x 2_5000 to 0x2_5FFF.

Table 14-3. Module Memory Map (continued)

Offset

Name

Access1

Reset

Section/Page

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