MPC8540 datasheet(648/1302 Pages) FREESCALE

648 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-22

Freescale Semiconductor

Three-Speed Ethernet Controllers

GTSC

Graceful transmit stop complete. This interrupt is asserted following the completion of a graceful stop,

which was intitiated by setting either DMACTRL[GTS] or TCTRL[TFC_PAUSE]. Graceful stop means

that the transmitter is put into a pause state after completion of the frame currently being transmitted.

0 Graceful transmit stop not complete or not initiated

1 Graceful transmit stop completed

BABT

Babbling transmit error. This bit indicates that the transmitted frame length has exceeded the value in

the MAC’s Maximum Frame Length register and MACCFG2[Huge Frame] is cleared. Frame truncation

occurs when this condition occurs. TxBD[TXTRUNC] is set in the last TxBD (TxBD[L] is set) of the

frame.

0 Transmitted frame length not exceeding maximum frame length

1 Transmitted frame length exceeding maximum frame length

TXC

Transmit control interrupt. This bit indicates that a control frame was transmitted.

0 Control frame not transmitted

1 Control frame transmitted

TXE

Transmit error. This bit indicates that an error occurred on the transmitted channel that has caused

TSTAT[THLT] to be set by TSEC. This bit is set whenever any transmit error occurs that causes the

transmitter to halt (EBERR, LC, CRL/XDA, XFUN). It is not set if DMACTRL[WOP] is set and TSEC

runs out of TxBDs to process. In order to begin transmitting packets again, the user must clear

TSTAT[THLT].

0 No transmit channel error occurred

1 Transmit channel error occurred

TXB

Transmit buffer. This bit indicates that a transmit buffer descriptor was updated whose I (interrupt) bit

was set in its status word and was not the last buffer descriptor of the frame.

0 No transmit buffer descriptor updated

1 Transmit buffer descriptor updated

TXF

Transmit frame interrupt. This bit indicates that a frame was transmitted and that the last corresponding

transmit buffer descriptor (TxBD) was updated. This only occurs if the I (interrupt) bit in the status word

of the buffer descriptor is set.

0 No frame transmitted/TxBD not updated

1 Frame transmitted/TxBD updated

—

Reserved

Late collision. This bit indicates that a collision occurred beyond the collision window (slot time) in

half-duplex mode. The frame is truncated with a bad CRC and the remainder of the frame is discarded.

0 No late collision occurred

1 Late collision occurred

CRL/

XDA

Collision retry limit/excessive defer abort. This bit indicates either one of two conditions occurred while

attempting to transmit a frame: 1) the number of successive transmission collisions has exceeded the

MAC’s HAFDUP[Retransmission Maximum] count or 2) an excessive defer abort condition has

occurred. An excessive defer abort condition occurs when the TSEC waits more than 3036 bytes while

attempting to send a frame and HAFDUP[EXCESS_DEFER] is 0. The TxBD[DEF] or OSTBD[DEF] is

also set. In either case the frame is discarded without being transmitted and the TSEC is halted

(TSTAT[THLT] is set). The CRL or XDA condition can only occur while in half-duplex mode.

0 Successive transmission collisions do not exceed maximum and no excessive defer abort condition

has occurred.

1 Successive transmission collisions exceed maximum or an excessive defer abort condition has

occurred.

Table 14-4. IEVENT Field Descriptions (continued)

Bits

Name

Description

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