MPC8540 datasheet(647/1302 Pages) FREESCALE

647 / 1302 page

Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-21

Table 14-4 describes the fields of the IEVENT register.

BABR RXC

BSY

EBERR

MSRO GTSC BABT

TXC

TXE

TXB

TXF

CRL/

XDA

XFUN

Reset

0000_0000_0000_0000

RXB

GRSC

RXF

Reset

0000_0000_0000_0000

Offset

TSEC1:0x2_4010; TSEC2:0x2_5010

Figure 14-6. IEVENT Register Definition

Table 14-4. IEVENT Field Descriptions

Bits

Name

Description

BABR

Babbling receive error. This bit indicates that a frame was received with length in excess of the MAC’s

maximum frame length register while MACCFG2[Huge Frame] is set.

0 Excessive frame not received

1 Excessive frame received

RXC

Receive control interrupt. A control frame was received. If MACCFG1[Rx_Flow] is set, a pause

operation is performed lasting for the duration specified in the received pause control frame and

beginning when the frame was received.

0 Control frame not received

1 Control frame received

BSY

Busy condition interrupt. Indicates that a frame was received and discarded due to a lack of buffers.

When IEVENT[BSY] is set RSTAT[QHLT] is also set. In order to begin receiving packets again, the user

must clear RSTAT[QHLT]. This bit and RSTAT[QHLT] are set whenever the TSEC reads an RxBD with

its Empty field cleared.

0 No frame received and discarded

1 Frame received and discarded

EBERR

Ethernet bus error. This bit indicates that a system bus error for a memory read occurred while a DMA

transaction was underway. If the EBERR is set while transmission is in progress, the DMA stops

sending data to the Tx FIFO which eventually causes an underrun error (XFUN) and TSTAT[THLT] is

set. If the EBERR is set while receiving a frame, the DMA discards the frame and RSTAT[QHLT] is set.

0 No system bus error occurred

1 System bus error occurred

4—

Reserved

MSRO

MSTAT Register Overflow. This interrupt is asserted if the count for one of the MSTAT registers has

exceeded the size of the register.

0 MSTAT count not exceeding register size

1 MSTAT count exceeds register size

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