MPC8540 datasheet(650/1302 Pages) FREESCALE

650 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-24

Freescale Semiconductor

Three-Speed Ethernet Controllers

Table 14-5 describes the fields of the IMASK register.

14.5.3.1.3 Error Disabled Register (EDIS)

The error disabled register, shown in Figure 14-8, controls error reporting by the TSEC. The

IEVENT bit corresponding to an error will not be set if the error is disabled in EDIS.

Table 14-5. IMASK Field Descriptions

Bits

Name

Description

BREN

Babbling receiver interrupt enable

RXCEN

Receive control interrupt enable

BSYEN

Busy interrupt enable

EBERREN

Ethernet controller bus error enable

4—

Reserved

MSROEN

MSTAT register overflow interrupt enable

GTSCEN

Graceful transmit stop complete interrupt enable

BTEN

Babbling transmitter interrupt enable

TXCEN

Transmit control interrupt enable

TXEEN

Transmit error interrupt enable

TXBEN

Transmit buffer interrupt enable

TXFEN

Transmit frame interrupt enable

—

Reserved

LCEN

Late collision enable

CRL/XDAEN

Collision retry limit/excessive defer enable

XFUNEN

Transmit FIFO underrun enable

RXBEN

Receive buffer interrupt enable

17–22

—

Reserved

GRSCEN

Graceful receive stop complete interrupt enable

RXFEN

Receive frame interrupt enable

25–31

—

Reserved

R0 0

BSYDIS EBERRDIS

000 00 0 0 0 0

LCDIS

0 0 0 0 0 000 000 000 000 0

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4018; TSEC2:0x2_5018

Figure 14-8.

Error Disabled Register (EDIS)

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