MPC8540 datasheet(651/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-25

Table 14-6 describes the fields of the EDIS register.

14.5.3.1.4 Ethernet Control Register (ECNTRL)

ECNTRL, shown in Figure 14-9, is used to reset, configure, and initialize the TSEC.

Table 14-7 describes the fields of the ECNTRL register.

Table 14-6. EDIS Field Descriptions

Bits

Name

Description

0–1

—

Reserved

BSYDIS

Busy disable

0 Allow TSEC to report IEVENT[BSY] status and halt buffer descriptor queue if BSY

condition occurs.

1 Do not set IEVENT[BSY] and do not halt buffer descriptor queue if BSY condition occurs.

EBERRDIS

Ethernet controller bus error disable

0 Allow TSEC to report IEVENT[EBERR] status and halt buffer descriptor queue if EBERR

condition occurs.

1 Do not set IEVENT[EBERR] and do not halt buffer descriptor queue if EBERR condition

occurs.

4–12

—

Reserved

LCDIS

Late collision disable

0 Allow TSEC to report IEVENT[LC] status, set the buffer descriptor LC field, and halt buffer

descriptor queue if LC condition occurs.

1 Do not set IEVENT[LC] nor the buffer Descriptor LC field, and do not halt buffer descriptor

queue if LC condition occurs.

14–31

—

Reserved

016

R 0 0 0 0 000 00 00 000 00 0

CLRCNT AUTOZ STEN

00 000 0 TBIM RPM

R100M

00 0

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4020; TSEC2:0x2_5020

Figure 14-9. ECNTRL Register Definition

Table 14-7. ECNTRL Field Descriptions

Bits

Name

Description

0–16

—

Reserved

CLRCNT Clear all statistics counters

0 Allow MSTAT counters to continue to increment.

1 Reset all MSTAT counters.

This bit is self-resetting.

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