MPC8540 datasheet(652/1302 Pages) FREESCALE

652 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-26

Freescale Semiconductor

Three-Speed Ethernet Controllers

14.5.3.1.5 Minimum Frame Length Register (MINFLR)

MINFLR is written by the user. It tells TSEC the smallest packet to accept and place in a receive

buffer pointed to by the RxBD. Figure 14-10 shows the MINFLR register.

AUTOZ

Automatically zero addressed statistical counter values, input to MSTAT module.

0 The user must write the addressed counter zero after a host read.

1 The addressed counter value is zeroed on a host read.

This is a steady state signal and must be set prior to enabling the Ethernet controller and must not

be changed without proper care.

STEN

Statistics enabled, input to MSTAT module.

0 Statistics not enabled

1 Enables internal counters to update

This is a steady state signal and must be set prior to enabling the Ethernet controller and must not

be changed without proper care.

20–25

—

Reserved

TBIM

Ten-bit interface mode. If this bit is set, ten-bit interface mode is enabled. This bit can be signal

configured at reset to set or clear using the TSECn_GTX_CLK signal.

0 GMII or MII mode interface

1 TBI mode interface

RPM

Reduced signal mode. If this bit is set, a reduced signal interface is expected. ECNTRL[TBI Mode]

selects GMII or TBI. If RPM is selected, the MAC must be in GMII or TBI mode (RMII is not

supported). This register can be signal configured at reset to 0 or 1 with the EC_MDC signal.

0 GMII or TBI in non-reduced signal mode configuration

1 RGMII or RTBI reduced signal mode

R100M

RGMII 100 mode. This bit is ignored unless RPM is set and MACCFG2[I/F Mode] is assigned to

10/100 (01). If this bit is set, the TSEC interface is in 100 Mbps speed.

0 RGMII is in 10 Mbps mode

1 RGMII is in 100 Mbps mode

29–31

—

Reserved

24 25

R 0

000

MINFLR

Reset

0000_0000_0000_0000_0000_0000_0100_0000

Offset

TSEC1:0x2_4024; TSEC2:0x2_502

Figure 14-10. MINFLR Register Definition

Table 14-7. ECNTRL Field Descriptions (continued)

Bits

Name

Description

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