MPC8540 datasheet(654/1302 Pages) FREESCALE

654 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

14-28

Freescale Semiconductor

Three-Speed Ethernet Controllers

14.5.3.1.7 DMA Control Register (DMACTRL)

DMACTRL, shown in Figure 14-12, is used to configure the DMA block. register.

Table 14-10 describes the fields of the DMACTRL register.

023

R 0 00 00 00 00 00 00 00 00 00 00 0 0

TDSEN TBDSEN

GRS GTS

WWR WOP

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_402C; TSEC2:0x2_502C

Figure 14-12. DMACTRL Register Definition

Table 14-10. DMACTRL Field Descriptions

Bits

Name

Description

0–23

—

Reserved

TDSEN

Tx Data snoop enable

0 Disables snooping of all transmit frames from memory.

1 Enables snooping of all transmit frames from memory.

TBDSEN TxBD snoop enable

0 Disables snooping of all transmit BD memory accesses.

1 Enables snooping of all transmit BD memory accesses.

—

Reserved

GRS

Graceful receive stop. If this bit is set, the Ethernet controller stops receiving frames following completion

of the frame currently being received, that is, after a valid end of frame was received. The buffer of the

receive frame associated with the EOF is closed and the IEVENT[GRSC] is set. Because the MAC’s

receive enable bit (MACCFG[Rx_EN]) may still be set, the MAC may continue to receive but the TSEC

ignores the receive data until GRS is cleared. If this bit is cleared, the TSEC scans the input data stream

for the start of a new frame (preamble sequence and start of frame delimiter) and the first valid frame

received uses the next RxBD.

If GRS is set, the user must monitor the graceful receive stop complete (GRSC) bit in the IEVENT

and can write to receive registers that are accessible to both user and the TSEC hardware without fear

of conflict.

0 TSEC scans input data stream for valid frame.

1 TSEC stops receiving frames following completion of current frame.

GTS

Graceful transmit stop. If this bit is set, the Ethernet controller stops transmission after the completion of

any frame that is currently being transmitted and the GTSC interrupt in the IEVENT register is asserted.

If frame transmission is not currently underway, the GTSC interrupt is asserted immediately. Once

transmission has completed, a “restart” can be accomplished by clearing GTS.

0 Controller continues.

1 Controller stops transmission after completion of current frame.

—

Reserved

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