MPC8540 datasheet(657/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

14-31

Table 14-12 describes the fields of the FIFO_PAUSE_CTRL register.

14.5.3.2.2 FIFO Transmit Threshold Register (FIFO_TX_THR)

The main purpose of the threshold register is to trigger the unloading of FIFO data to the PHY. It

represents the numerical SRAM entry (0-511 for 2-Kbyte FIFO) to trigger the threshold function.

If the number of valid entries in the FIFO is equal to or greater than the threshold register,

transmission can begin. This register is read/write by software and is initialized to

0000_0000_0000_0000_0000_0001_0000_0000 at system reset. Figure 14-15 shows the

FIFO_TX_THR register.

Reset

0000_0000_0000_0000

TFC_PAUSE_EN

Reset

0000_0000_0000_0000

Offset

TSEC1:0x2_404C; TSEC2:0x2_504C

Figure 14-14. FIFO_PAUSE_CTRL Register Definition

Table 14-12. FIFO_PAUSE_CTRL Field Descriptions

Bits

Name

Description

0–29

—

Reserved

TFC_PAUSE_EN TFC_PAUSE enable. This bit enables the ability to transmit a pause control frame by

setting the TCTRL[TFC_PAUSE] bit. This bit is cleared at reset.

0 Pause control frame transmission disabled.

1 Pause control frame transmission enabled.

—

Reserved

22 23

R 0

000

FIFO_TX_THR

Reset

0000_0000_0000_0000_0000_0001_0000_0000

Offset

TSEC1:0x2_408C; TSEC2:0x2_508C

Figure 14-15. FIFO_TX_THR Register Definition

MPC8540 Datasheet(PDF) 657 Page - Freescale Semiconductor, Inc

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